Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9f4f04ba authored by Joakim Tjernlund's avatar Joakim Tjernlund Committed by Benjamin Herrenschmidt
Browse files

powerpc/8xx: Always pin kernel instruction TLB 



Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.

Signed-off-by: default avatarJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 004b3506

arch/powerpc/kernel/head_8xx.S

+4 −4
Original line number Original line Diff line number Diff line
@@ -768,12 +768,12 @@ start_here: 
 */

 */

initial_mmu:

initial_mmu:

	tlbia			/* Invalidate all TLB entries */

	tlbia			/* Invalidate all TLB entries */

#ifdef CONFIG_PIN_TLB

/* Always pin the first 8 MB ITLB to prevent ITLB

   misses while mucking around with SRR0/SRR1 in asm

*/

	lis	r8, MI_RSV4I@h

	lis	r8, MI_RSV4I@h

	ori	r8, r8, 0x1c00

	ori	r8, r8, 0x1c00

#else



	li	r8, 0

#endif

	mtspr	SPRN_MI_CTR, r8	/* Set instruction MMU control */

	mtspr	SPRN_MI_CTR, r8	/* Set instruction MMU control */





#ifdef CONFIG_PIN_TLB

#ifdef CONFIG_PIN_TLB