ARM: 6447/3: sa1100: Put nanoEngine support back in the kernel (9f15d2ca) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm/mach-sa1100/Kconfig

+8 −0

Original line number	Diff line number	Diff line
		@@ -118,6 +118,14 @@ config SA1100_LART
		(also known as the LART). See <http://www.lartmaker.nl/> for
		information on the LART.

		config SA1100_NANOENGINE
		bool "nanoEngine"
		select CPU_FREQ_SA1110
		help
		Say Y here if you are using the Bright Star Engineering nanoEngine.
		See <http://www.brightstareng.com/arm/nanoeng.htm> for information
		on the BSE nanoEngine.

		config SA1100_PLEB
		bool "PLEB"
		select CPU_FREQ_SA1100

arch/arm/mach-sa1100/Makefile

+2 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,8 @@ obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o
		obj-$(CONFIG_SA1100_LART) += lart.o
		led-$(CONFIG_SA1100_LART) += leds-lart.o

		obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o

		obj-$(CONFIG_SA1100_PLEB) += pleb.o

		obj-$(CONFIG_SA1100_SHANNON) += shannon.o

arch/arm/mach-sa1100/cpu-sa1110.c

+20 −13

Original line number	Diff line number	Diff line
		@@ -16,28 +16,24 @@
		*
		* The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
		*/
		#include <linux/moduleparam.h>
		#include <linux/types.h>
		#include <linux/kernel.h>
		#include <linux/sched.h>
		#include <linux/cpufreq.h>
		#include <linux/delay.h>
		#include <linux/init.h>
		#include <linux/io.h>
		#include <linux/kernel.h>
		#include <linux/moduleparam.h>
		#include <linux/types.h>

		#include <mach/hardware.h>
		#include <asm/cputype.h>
		#include <asm/mach-types.h>
		#include <asm/system.h>

		#include <mach/hardware.h>

		#include "generic.h"

		#undef DEBUG

		static struct cpufreq_driver sa1110_driver;

		struct sdram_params {
		const char name[16];
		const char name[20];
		u_char rows; /* bits */
		u_char cas_latency; /* cycles */
		u_char tck; /* clock cycle time (ns) */
		@@ -107,6 +103,15 @@ static struct sdram_params sdram_tbl[] __initdata = {
		.twr = 8,
		.refresh = 64000,
		.cas_latency = 3,
		}, { /* Micron MT48LC8M16A2TG-75 */
		.name = "MT48LC8M16A2TG-75",
		.rows = 12,
		.tck = 8,
		.trcd = 20,
		.trp = 20,
		.twr = 8,
		.refresh = 64000,
		.cas_latency = 3,
		},
		};

		@@ -336,7 +341,9 @@ static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
		return 0;
		}

		static struct cpufreq_driver sa1110_driver = {
		/* sa1110_driver needs __refdata because it must remain after init registers
		* it with cpufreq_register_driver() */
		static struct cpufreq_driver sa1110_driver __refdata = {
		.flags = CPUFREQ_STICKY,
		.verify = sa11x0_verify_speed,
		.target = sa1110_target,
		@@ -369,14 +376,14 @@ static int __init sa1110_clk_init(void)
		if (!name[0]) {
		if (machine_is_assabet())
		name = "TC59SM716-CL3";

		if (machine_is_pt_system3())
		name = "K4S641632D";

		if (machine_is_h3100())
		name = "KM416S4030CT";
		if (machine_is_jornada720())
		name = "K4S281632B-1H";
		if (machine_is_nanoengine())
		name = "MT48LC8M16A2TG-75";
		}

		sdram = sa1110_find_sdram(name);

arch/arm/mach-sa1100/nanoengine.c

0 → 100644

+112 −0

Original line number	Diff line number	Diff line
		/*
		* linux/arch/arm/mach-sa1100/nanoengine.c
		*
		* Bright Star Engineering's nanoEngine board init code.
		*
		* Copyright (C) 2009 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		*/

		#include <linux/init.h>
		#include <linux/kernel.h>
		#include <linux/mtd/mtd.h>
		#include <linux/mtd/partitions.h>
		#include <linux/root_dev.h>

		#include <asm/mach-types.h>
		#include <asm/setup.h>

		#include <asm/mach/arch.h>
		#include <asm/mach/flash.h>
		#include <asm/mach/map.h>
		#include <asm/mach/serial_sa1100.h>

		#include <mach/hardware.h>

		#include "generic.h"

		/* Flash bank 0 */
		static struct mtd_partition nanoengine_partitions[] = {
		{
		.name = "nanoEngine boot firmware and parameter table",
		.size = 0x00010000, /* 32K */
		.offset = 0,
		.mask_flags = MTD_WRITEABLE,
		}, {
		.name = "kernel/initrd reserved",
		.size = 0x002f0000,
		.offset = 0x00010000,
		.mask_flags = MTD_WRITEABLE,
		}, {
		.name = "experimental filesystem allocation",
		.size = 0x00100000,
		.offset = 0x00300000,
		.mask_flags = MTD_WRITEABLE,
		}
		};

		static struct flash_platform_data nanoengine_flash_data = {
		.map_name = "jedec_probe",
		.parts = nanoengine_partitions,
		.nr_parts = ARRAY_SIZE(nanoengine_partitions),
		};

		static struct resource nanoengine_flash_resources[] = {
		{
		.start = SA1100_CS0_PHYS,
		.end = SA1100_CS0_PHYS + SZ_32M - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = SA1100_CS1_PHYS,
		.end = SA1100_CS1_PHYS + SZ_32M - 1,
		.flags = IORESOURCE_MEM,
		}
		};

		static struct map_desc nanoengine_io_desc[] __initdata = {
		{
		/* System Registers */
		.virtual = 0xf0000000,
		.pfn = __phys_to_pfn(0x10000000),
		.length = 0x00100000,
		.type = MT_DEVICE
		}, {
		/* Internal PCI Config Space */
		.virtual = 0xf1000000,
		.pfn = __phys_to_pfn(0x18A00000),
		.length = 0x00100000,
		.type = MT_DEVICE
		}
		};

		static void __init nanoengine_map_io(void)
		{
		sa1100_map_io();
		iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));

		sa1100_register_uart(0, 1);
		sa1100_register_uart(1, 2);
		sa1100_register_uart(2, 3);
		Ser1SDCR0 \|= SDCR0_UART;
		/* disable IRDA -- UART2 is used as a normal serial port */
		Ser2UTCR4 = 0;
		Ser2HSCR0 = 0;
		}

		static void __init nanoengine_init(void)
		{
		sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
		ARRAY_SIZE(nanoengine_flash_resources));
		}

		MACHINE_START(NANOENGINE, "BSE nanoEngine")
		.boot_params = 0xc0000000,
		.map_io = nanoengine_map_io,
		.init_irq = sa1100_init_irq,
		.timer = &sa1100_timer,
		.init_machine = nanoengine_init,
		MACHINE_END