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Commit 9ed0dca7 authored by Shefali Jain's avatar Shefali Jain
Browse files

ARM: dts: msm: Add the CMN BLK PLL node for QCS405 



Add cmn_blk_pll node to use the CMN BLK PLL driver.

Change-Id: I1efad217ad2bff16e25445c9ed56b16350df31a1
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 17eb0120

arch/arm64/boot/dts/qcom/qcs405.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include "skeleton64.dtsi"

#include <dt-bindings/clock/qcom,gcc-qcs405.h>

#include <dt-bindings/clock/qcom,cpu-qcs405.h>

#include <dt-bindings/clock/qcom,cmn-blk-pll.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -315,6 +316,19 @@ 
		#reset-cells = <1>;

	};



	clock_cmn_blk_pll: qcom,cmn_blk_pll@2f780 {

		compatible = "qcom,cmn_blk_pll";

		reg = <0x2f780 0x4>;

		reg-names = "cmn_blk";

		clocks = <&clock_gcc GCC_BIAS_PLL_MISC_RESET_CLK>,

			<&clock_gcc GCC_BIAS_PLL_AHB_CLK>,

			<&clock_gcc GCC_BIAS_PLL_AON_CLK>;

		clock-names = "misc_reset_clk", "ahb_clk", "aon_clk";

		resets = <&clock_gcc GCC_BIAS_PLL_BCR>;

		reset-names = "cmn_blk_pll_reset";

		#clock-cells = <1>;

	};



	clock_gcc_mdss: qcom,gcc-mdss@1800000 {

		compatible = "qcom,gcc-mdss-qcs405";

		reg = <0x1800000 0x80000>;