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Commit 9eb80226 authored by Laxminath Kasam's avatar Laxminath Kasam
Browse files

asoc: bolero: fix pop issue at start of record 



Observe pop at start of recording. Change the
order of HPF setting in decimator enable path
and update freq_change bit for HPF corner frequency change.

Change-Id: I6257671224a792a2afd71209fdc4e0102a83ced8
Signed-off-by: default avatarLaxminath Kasam <lkasam@codeaurora.org>
parent 14f47cc8

asoc/codecs/bolero/tx-macro.c

+31 −9
Original line number Diff line number Diff line
@@ -296,7 +296,7 @@ static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 
	struct hpf_work *hpf_work = NULL;

	struct tx_macro_priv *tx_priv = NULL;

	struct snd_soc_codec *codec = NULL;

	u16 dec_cfg_reg = 0;

	u16 dec_cfg_reg = 0, hpf_gate_reg = 0;

	u8 hpf_cut_off_freq = 0;



	hpf_delayed_work = to_delayed_work(work);
@@ -307,12 +307,18 @@ static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 


	dec_cfg_reg = BOLERO_CDC_TX0_TX_PATH_CFG0 +

			TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator;

	hpf_gate_reg = BOLERO_CDC_TX0_TX_PATH_SEC2 +

			TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator;



	dev_dbg(codec->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n",

		__func__, hpf_work->decimator, hpf_cut_off_freq);



	snd_soc_update_bits(codec, dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,

			    hpf_cut_off_freq << 5);

	snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x02);

	/* Minimum 1 clk cycle delay is required as per HW spec */

	usleep_range(1000, 1010);

	snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x00);

}



static void tx_macro_mute_update_callback(struct work_struct *work)
@@ -573,6 +579,13 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 


	switch (event) {

	case SND_SOC_DAPM_PRE_PMU:

		/* Enable TX PGA Mute */

		snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x10);

		break;

	case SND_SOC_DAPM_POST_PMU:

		snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x20, 0x20);

		snd_soc_update_bits(codec, hpf_gate_reg, 0x01, 0x00);



		hpf_cut_off_freq = (snd_soc_read(codec, dec_cfg_reg) &

				   TX_HPF_CUT_OFF_FREQ_MASK) >> 5;

		tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq =
@@ -582,21 +595,21 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
			snd_soc_update_bits(codec, dec_cfg_reg,

					    TX_HPF_CUT_OFF_FREQ_MASK,

					    CF_MIN_3DB_150HZ << 5);

		/* Enable TX PGA Mute */

		snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x10);

		break;

	case SND_SOC_DAPM_POST_PMU:

		snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x20, 0x20);

		snd_soc_update_bits(codec, hpf_gate_reg, 0x01, 0x00);



		/* schedule work queue to Remove Mute */

		schedule_delayed_work(&tx_priv->tx_mute_dwork[decimator].dwork,

				      msecs_to_jiffies(tx_unmute_delay));

		if (tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq !=

							CF_MIN_3DB_150HZ)

							CF_MIN_3DB_150HZ) {

			schedule_delayed_work(

					&tx_priv->tx_hpf_work[decimator].dwork,

					msecs_to_jiffies(300));

			snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x02);

			/*

			 * Minimum 1 clk cycle delay is required as per HW spec

			 */

			usleep_range(1000, 1010);

			snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x00);

		}

		/* apply gain after decimator is enabled */

		snd_soc_write(codec, tx_gain_ctl_reg,

			      snd_soc_read(codec, tx_gain_ctl_reg));
@@ -611,6 +624,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				snd_soc_update_bits(codec, dec_cfg_reg,

						    TX_HPF_CUT_OFF_FREQ_MASK,

						    hpf_cut_off_freq << 5);

				snd_soc_update_bits(codec, hpf_gate_reg,

						0x02, 0x02);

				/*

				 * Minimum 1 clk cycle delay is required

				 * as per HW spec

				 */

				usleep_range(1000, 1010);

				snd_soc_update_bits(codec, hpf_gate_reg,

						0x02, 0x00);

			}

		}

		cancel_delayed_work_sync(

asoc/codecs/bolero/va-macro.c

+32 −10
Original line number Diff line number Diff line
@@ -245,7 +245,7 @@ static void va_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 
	struct hpf_work *hpf_work;

	struct va_macro_priv *va_priv;

	struct snd_soc_codec *codec;

	u16 dec_cfg_reg;

	u16 dec_cfg_reg, hpf_gate_reg;

	u8 hpf_cut_off_freq;



	hpf_delayed_work = to_delayed_work(work);
@@ -256,12 +256,18 @@ static void va_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 


	dec_cfg_reg = BOLERO_CDC_VA_TX0_TX_PATH_CFG0 +

			VA_MACRO_TX_PATH_OFFSET * hpf_work->decimator;

	hpf_gate_reg = BOLERO_CDC_VA_TX0_TX_PATH_SEC2 +

			VA_MACRO_TX_PATH_OFFSET * hpf_work->decimator;



	dev_dbg(va_priv->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n",

		__func__, hpf_work->decimator, hpf_cut_off_freq);



	snd_soc_update_bits(codec, dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,

			    hpf_cut_off_freq << 5);

	snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x02);

	/* Minimum 1 clk cycle delay is required as per HW spec */

	usleep_range(1000, 1010);

	snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x00);

}



static void va_macro_mute_update_callback(struct work_struct *work)
@@ -512,15 +518,6 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 


	switch (event) {

	case SND_SOC_DAPM_PRE_PMU:

		hpf_cut_off_freq = (snd_soc_read(codec, dec_cfg_reg) &

				   TX_HPF_CUT_OFF_FREQ_MASK) >> 5;

		va_priv->va_hpf_work[decimator].hpf_cut_off_freq =

							hpf_cut_off_freq;



		if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)

			snd_soc_update_bits(codec, dec_cfg_reg,

					    TX_HPF_CUT_OFF_FREQ_MASK,

					    CF_MIN_3DB_150HZ << 5);

		/* Enable TX PGA Mute */

		snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x10);

		break;
@@ -529,6 +526,22 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
		snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x20, 0x20);

		snd_soc_update_bits(codec, hpf_gate_reg, 0x01, 0x00);



		hpf_cut_off_freq = (snd_soc_read(codec, dec_cfg_reg) &

				   TX_HPF_CUT_OFF_FREQ_MASK) >> 5;

		va_priv->va_hpf_work[decimator].hpf_cut_off_freq =

							hpf_cut_off_freq;



		if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {

			snd_soc_update_bits(codec, dec_cfg_reg,

					    TX_HPF_CUT_OFF_FREQ_MASK,

					    CF_MIN_3DB_150HZ << 5);

			snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x02);

			/*

			 * Minimum 1 clk cycle delay is required as per HW spec

			 */

			usleep_range(1000, 1010);

			snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x00);

		}

		/* schedule work queue to Remove Mute */

		schedule_delayed_work(&va_priv->va_mute_dwork[decimator].dwork,

				      msecs_to_jiffies(va_tx_unmute_delay));
@@ -551,6 +564,15 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				snd_soc_update_bits(codec, dec_cfg_reg,

						    TX_HPF_CUT_OFF_FREQ_MASK,

						    hpf_cut_off_freq << 5);

				snd_soc_update_bits(codec, hpf_gate_reg,

						    0x02, 0x02);

				/*

				 * Minimum 1 clk cycle delay is required

				 * as per HW spec

				 */

				usleep_range(1000, 1010);

				snd_soc_update_bits(codec, hpf_gate_reg,

						    0x02, 0x00);

			}

		}

		cancel_delayed_work_sync(