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Commit 9eb2eb8c authored by Sascha Hauer's avatar Sascha Hauer
Browse files

MX31 clkdev support 



This patch adds clkdev support for i.MX31. This is done in a
similar way done previously for i.MX27

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent 9a51157b

arch/arm/mach-mx3/clock.c

+203 −729

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-mx3/crm_regs.h

+0 −153
Original line number Diff line number Diff line
@@ -91,47 +91,6 @@ 
#define MXC_CCM_PDR0_MCU_PODF_OFFSET            0

#define MXC_CCM_PDR0_MCU_PODF_MASK              0x7



#define MXC_CCM_PDR0_HSP_DIV_1                  (0x0 << 11)

#define MXC_CCM_PDR0_HSP_DIV_2                  (0x1 << 11)

#define MXC_CCM_PDR0_HSP_DIV_3                  (0x2 << 11)

#define MXC_CCM_PDR0_HSP_DIV_4                  (0x3 << 11)

#define MXC_CCM_PDR0_HSP_DIV_5                  (0x4 << 11)

#define MXC_CCM_PDR0_HSP_DIV_6                  (0x5 << 11)

#define MXC_CCM_PDR0_HSP_DIV_7                  (0x6 << 11)

#define MXC_CCM_PDR0_HSP_DIV_8                  (0x7 << 11)



#define MXC_CCM_PDR0_IPG_DIV_1                  (0x0 << 6)

#define MXC_CCM_PDR0_IPG_DIV_2                  (0x1 << 6)

#define MXC_CCM_PDR0_IPG_DIV_3                  (0x2 << 6)

#define MXC_CCM_PDR0_IPG_DIV_4                  (0x3 << 6)



#define MXC_CCM_PDR0_MAX_DIV_1                  (0x0 << 3)

#define MXC_CCM_PDR0_MAX_DIV_2                  (0x1 << 3)

#define MXC_CCM_PDR0_MAX_DIV_3                  (0x2 << 3)

#define MXC_CCM_PDR0_MAX_DIV_4                  (0x3 << 3)

#define MXC_CCM_PDR0_MAX_DIV_5                  (0x4 << 3)

#define MXC_CCM_PDR0_MAX_DIV_6                  (0x5 << 3)

#define MXC_CCM_PDR0_MAX_DIV_7                  (0x6 << 3)

#define MXC_CCM_PDR0_MAX_DIV_8                  (0x7 << 3)



#define MXC_CCM_PDR0_NFC_DIV_1                  (0x0 << 8)

#define MXC_CCM_PDR0_NFC_DIV_2                  (0x1 << 8)

#define MXC_CCM_PDR0_NFC_DIV_3                  (0x2 << 8)

#define MXC_CCM_PDR0_NFC_DIV_4                  (0x3 << 8)

#define MXC_CCM_PDR0_NFC_DIV_5                  (0x4 << 8)

#define MXC_CCM_PDR0_NFC_DIV_6                  (0x5 << 8)

#define MXC_CCM_PDR0_NFC_DIV_7                  (0x6 << 8)

#define MXC_CCM_PDR0_NFC_DIV_8                  (0x7 << 8)



#define MXC_CCM_PDR0_MCU_DIV_1                  0x0

#define MXC_CCM_PDR0_MCU_DIV_2                  0x1

#define MXC_CCM_PDR0_MCU_DIV_3                  0x2

#define MXC_CCM_PDR0_MCU_DIV_4                  0x3

#define MXC_CCM_PDR0_MCU_DIV_5                  0x4

#define MXC_CCM_PDR0_MCU_DIV_6                  0x5

#define MXC_CCM_PDR0_MCU_DIV_7                  0x6

#define MXC_CCM_PDR0_MCU_DIV_8                  0x7



#define MXC_CCM_PDR1_USB_PRDF_OFFSET            30

#define MXC_CCM_PDR1_USB_PRDF_MASK              (0x3 << 30)

#define MXC_CCM_PDR1_USB_PODF_OFFSET            27
@@ -152,118 +111,6 @@ 
/* Bit definitions for RCSR */

#define MXC_CCM_RCSR_NF16B			0x80000000



/* Bit definitions for both MCU, USB and SR PLL control registers */

#define MXC_CCM_PCTL_BRM                        0x80000000

#define MXC_CCM_PCTL_PD_OFFSET                  26

#define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)

#define MXC_CCM_PCTL_MFD_OFFSET                 16

#define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)

#define MXC_CCM_PCTL_MFI_OFFSET                 10

#define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)

#define MXC_CCM_PCTL_MFN_OFFSET                 0

#define MXC_CCM_PCTL_MFN_MASK                   0x3FF



#define MXC_CCM_CGR0_SD_MMC1_OFFSET             0

#define MXC_CCM_CGR0_SD_MMC1_MASK               (0x3 << 0)

#define MXC_CCM_CGR0_SD_MMC2_OFFSET             2

#define MXC_CCM_CGR0_SD_MMC2_MASK               (0x3 << 2)

#define MXC_CCM_CGR0_GPT_OFFSET                 4

#define MXC_CCM_CGR0_GPT_MASK                   (0x3 << 4)

#define MXC_CCM_CGR0_EPIT1_OFFSET               6

#define MXC_CCM_CGR0_EPIT1_MASK                 (0x3 << 6)

#define MXC_CCM_CGR0_EPIT2_OFFSET               8

#define MXC_CCM_CGR0_EPIT2_MASK                 (0x3 << 8)

#define MXC_CCM_CGR0_IIM_OFFSET                 10

#define MXC_CCM_CGR0_IIM_MASK                   (0x3 << 10)

#define MXC_CCM_CGR0_ATA_OFFSET                 12

#define MXC_CCM_CGR0_ATA_MASK                   (0x3 << 12)

#define MXC_CCM_CGR0_SDMA_OFFSET                14

#define MXC_CCM_CGR0_SDMA_MASK                  (0x3 << 14)

#define MXC_CCM_CGR0_CSPI3_OFFSET               16

#define MXC_CCM_CGR0_CSPI3_MASK                 (0x3 << 16)

#define MXC_CCM_CGR0_RNG_OFFSET                 18

#define MXC_CCM_CGR0_RNG_MASK                   (0x3 << 18)

#define MXC_CCM_CGR0_UART1_OFFSET               20

#define MXC_CCM_CGR0_UART1_MASK                 (0x3 << 20)

#define MXC_CCM_CGR0_UART2_OFFSET               22

#define MXC_CCM_CGR0_UART2_MASK                 (0x3 << 22)

#define MXC_CCM_CGR0_SSI1_OFFSET                24

#define MXC_CCM_CGR0_SSI1_MASK                  (0x3 << 24)

#define MXC_CCM_CGR0_I2C1_OFFSET                26

#define MXC_CCM_CGR0_I2C1_MASK                  (0x3 << 26)

#define MXC_CCM_CGR0_I2C2_OFFSET                28

#define MXC_CCM_CGR0_I2C2_MASK                  (0x3 << 28)

#define MXC_CCM_CGR0_I2C3_OFFSET                30

#define MXC_CCM_CGR0_I2C3_MASK                  (0x3 << 30)



#define MXC_CCM_CGR1_HANTRO_OFFSET              0

#define MXC_CCM_CGR1_HANTRO_MASK                (0x3 << 0)

#define MXC_CCM_CGR1_MEMSTICK1_OFFSET           2

#define MXC_CCM_CGR1_MEMSTICK1_MASK             (0x3 << 2)

#define MXC_CCM_CGR1_MEMSTICK2_OFFSET           4

#define MXC_CCM_CGR1_MEMSTICK2_MASK             (0x3 << 4)

#define MXC_CCM_CGR1_CSI_OFFSET                 6

#define MXC_CCM_CGR1_CSI_MASK                   (0x3 << 6)

#define MXC_CCM_CGR1_RTC_OFFSET                 8

#define MXC_CCM_CGR1_RTC_MASK                   (0x3 << 8)

#define MXC_CCM_CGR1_WDOG_OFFSET                10

#define MXC_CCM_CGR1_WDOG_MASK                  (0x3 << 10)

#define MXC_CCM_CGR1_PWM_OFFSET                 12

#define MXC_CCM_CGR1_PWM_MASK                   (0x3 << 12)

#define MXC_CCM_CGR1_SIM_OFFSET                 14

#define MXC_CCM_CGR1_SIM_MASK                   (0x3 << 14)

#define MXC_CCM_CGR1_ECT_OFFSET                 16

#define MXC_CCM_CGR1_ECT_MASK                   (0x3 << 16)

#define MXC_CCM_CGR1_USBOTG_OFFSET              18

#define MXC_CCM_CGR1_USBOTG_MASK                (0x3 << 18)

#define MXC_CCM_CGR1_KPP_OFFSET                 20

#define MXC_CCM_CGR1_KPP_MASK                   (0x3 << 20)

#define MXC_CCM_CGR1_IPU_OFFSET                 22

#define MXC_CCM_CGR1_IPU_MASK                   (0x3 << 22)

#define MXC_CCM_CGR1_UART3_OFFSET               24

#define MXC_CCM_CGR1_UART3_MASK                 (0x3 << 24)

#define MXC_CCM_CGR1_UART4_OFFSET               26

#define MXC_CCM_CGR1_UART4_MASK                 (0x3 << 26)

#define MXC_CCM_CGR1_UART5_OFFSET               28

#define MXC_CCM_CGR1_UART5_MASK                 (0x3 << 28)

#define MXC_CCM_CGR1_OWIRE_OFFSET               30

#define MXC_CCM_CGR1_OWIRE_MASK                 (0x3 << 30)



#define MXC_CCM_CGR2_SSI2_OFFSET                0

#define MXC_CCM_CGR2_SSI2_MASK                  (0x3 << 0)

#define MXC_CCM_CGR2_CSPI1_OFFSET               2

#define MXC_CCM_CGR2_CSPI1_MASK                 (0x3 << 2)

#define MXC_CCM_CGR2_CSPI2_OFFSET               4

#define MXC_CCM_CGR2_CSPI2_MASK                 (0x3 << 4)

#define MXC_CCM_CGR2_GACC_OFFSET                6

#define MXC_CCM_CGR2_GACC_MASK                  (0x3 << 6)

#define MXC_CCM_CGR2_EMI_OFFSET                 8

#define MXC_CCM_CGR2_EMI_MASK                   (0x3 << 8)

#define MXC_CCM_CGR2_RTIC_OFFSET                10

#define MXC_CCM_CGR2_RTIC_MASK                  (0x3 << 10)

#define MXC_CCM_CGR2_FIRI_OFFSET                12

#define MXC_CCM_CGR2_FIRI_MASK                  (0x3 << 12)

#define MXC_CCM_CGR2_IPMUX1_OFFSET              14

#define MXC_CCM_CGR2_IPMUX1_MASK                (0x3 << 14)

#define MXC_CCM_CGR2_IPMUX2_OFFSET              16

#define MXC_CCM_CGR2_IPMUX2_MASK                (0x3 << 16)



/* These new CGR2 bits are added in MX32 */

#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET	18

#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK		(0x3 << 18)

#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET	20

#define MXC_CCM_CGR2_APMSSICLKSEL_MASK		(0x3 << 20)

#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET	22

#define MXC_CCM_CGR2_APMPERCLKSEL_MASK		(0x3 << 22)

#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET		24

#define MXC_CCM_CGR2_MXCCLKENSEL_MASK		(0x1 << 24)

#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET		25

#define MXC_CCM_CGR2_CHIKCAMPEN_MASK		(0x1 << 25)

#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET		26

#define MXC_CCM_CGR2_OVRVPUBUSY_MASK		(0x1 << 26)

#define MXC_CCM_CGR2_APMENA_OFFSET		30

#define MXC_CCM_CGR2_AOMENA_MASK		(0x1 << 30)



/*

 * LTR0 register offsets

 */

arch/arm/plat-mxc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ config ARCH_MX2 
config ARCH_MX3

	bool "MX3-based"

	select CPU_V6

	select COMMON_CLKDEV

	help

	  This enables support for systems based on the Freescale i.MX3 family

drivers/dma/ipu/ipu_idmac.c

+1 −1
Original line number Diff line number Diff line
@@ -1649,7 +1649,7 @@ static int ipu_probe(struct platform_device *pdev) 
	}



	/* Get IPU clock */

	ipu_data.ipu_clk = clk_get(&pdev->dev, "ipu_clk");

	ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);

	if (IS_ERR(ipu_data.ipu_clk)) {

		ret = PTR_ERR(ipu_data.ipu_clk);

		goto err_clk_get;

drivers/video/mx3fb.c

+1 −1
Original line number Diff line number Diff line
@@ -493,7 +493,7 @@ static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel, 
        */

       dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk);



       ipu_clk = clk_get(mx3fb->dev, "ipu_clk");

       ipu_clk = clk_get(mx3fb->dev, NULL);

       div = clk_get_rate(ipu_clk) * 16 / pixel_clk;

       clk_put(ipu_clk);