Merge tag 'ib-mfd-mtd-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd (9e43486a) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/mtd/intel-spi.txt

0 → 100644

+88 −0

Original line number	Diff line number	Diff line
		Upgrading BIOS using intel-spi
		------------------------------

		Many Intel CPUs like Baytrail and Braswell include SPI serial flash host
		controller which is used to hold BIOS and other platform specific data.
		Since contents of the SPI serial flash is crucial for machine to function,
		it is typically protected by different hardware protection mechanisms to
		avoid accidental (or on purpose) overwrite of the content.

		Not all manufacturers protect the SPI serial flash, mainly because it
		allows upgrading the BIOS image directly from an OS.

		The intel-spi driver makes it possible to read and write the SPI serial
		flash, if certain protection bits are not set and locked. If it finds
		any of them set, the whole MTD device is made read-only to prevent
		partial overwrites. By default the driver exposes SPI serial flash
		contents as read-only but it can be changed from kernel command line,
		passing "intel-spi.writeable=1".

		Please keep in mind that overwriting the BIOS image on SPI serial flash
		might render the machine unbootable and requires special equipment like
		Dediprog to revive. You have been warned!

		Below are the steps how to upgrade MinnowBoard MAX BIOS directly from
		Linux.

		1) Download and extract the latest Minnowboard MAX BIOS SPI image
		[1]. At the time writing this the latest image is v92.

		2) Install mtd-utils package [2]. We need this in order to erase the SPI
		serial flash. Distros like Debian and Fedora have this prepackaged with
		name "mtd-utils".

		3) Add "intel-spi.writeable=1" to the kernel command line and reboot
		the board (you can also reload the driver passing "writeable=1" as
		module parameter to modprobe).

		4) Once the board is up and running again, find the right MTD partition
		(it is named as "BIOS"):

		# cat /proc/mtd
		dev: size erasesize name
		mtd0: 00800000 00001000 "BIOS"

		So here it will be /dev/mtd0 but it may vary.

		5) Make backup of the existing image first:

		# dd if=/dev/mtd0ro of=bios.bak
		16384+0 records in
		16384+0 records out
		8388608 bytes (8.4 MB) copied, 10.0269 s, 837 kB/s

		6) Verify the backup

		# sha1sum /dev/mtd0ro bios.bak
		fdbb011920572ca6c991377c4b418a0502668b73 /dev/mtd0ro
		fdbb011920572ca6c991377c4b418a0502668b73 bios.bak

		The SHA1 sums must match. Otherwise do not continue any further!

		7) Erase the SPI serial flash. After this step, do not reboot the
		board! Otherwise it will not start anymore.

		# flash_erase /dev/mtd0 0 0
		Erasing 4 Kibyte @ 7ff000 -- 100 % complete

		8) Once completed without errors you can write the new BIOS image:

		# dd if=MNW2MAX1.X64.0092.R01.1605221712.bin of=/dev/mtd0

		9) Verify that the new content of the SPI serial flash matches the new
		BIOS image:

		# sha1sum /dev/mtd0ro MNW2MAX1.X64.0092.R01.1605221712.bin
		9b4df9e4be2057fceec3a5529ec3d950836c87a2 /dev/mtd0ro
		9b4df9e4be2057fceec3a5529ec3d950836c87a2 MNW2MAX1.X64.0092.R01.1605221712.bin

		The SHA1 sums should match.

		10) Now you can reboot your board and observe the new BIOS starting up
		properly.

		References
		----------

		[1] https://firmware.intel.com/sites/default/files/MinnowBoard.MAX_.X64.92.R01.zip
		[2] http://www.linux-mtd.infradead.org/

drivers/mfd/lpc_ich.c

+131 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,7 @@
		* document number TBD : Wildcat Point-LP
		* document number TBD : 9 Series
		* document number TBD : Lewisburg
		* document number TBD : Apollo Lake SoC
		*/

		#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
		@@ -83,6 +84,17 @@
		#define ACPIBASE_GCS_OFF 0x3410
		#define ACPIBASE_GCS_END 0x3414

		#define SPIBASE_BYT 0x54
		#define SPIBASE_BYT_SZ 512
		#define SPIBASE_BYT_EN BIT(1)

		#define SPIBASE_LPT 0x3800
		#define SPIBASE_LPT_SZ 512
		#define BCR 0xdc
		#define BCR_WPD BIT(0)

		#define SPIBASE_APL_SZ 4096

		#define GPIOBASE_ICH0 0x58
		#define GPIOCTRL_ICH0 0x5C
		#define GPIOBASE_ICH6 0x48
		@@ -133,6 +145,12 @@ static struct resource gpio_ich_res[] = {
		},
		};

		static struct resource intel_spi_res[] = {
		{
		.flags = IORESOURCE_MEM,
		}
		};

		static struct mfd_cell lpc_ich_wdt_cell = {
		.name = "iTCO_wdt",
		.num_resources = ARRAY_SIZE(wdt_ich_res),
		@@ -147,6 +165,14 @@ static struct mfd_cell lpc_ich_gpio_cell = {
		.ignore_resource_conflicts = true,
		};


		static struct mfd_cell lpc_ich_spi_cell = {
		.name = "intel-spi",
		.num_resources = ARRAY_SIZE(intel_spi_res),
		.resources = intel_spi_res,
		.ignore_resource_conflicts = true,
		};

		/* chipset related info */
		enum lpc_chipsets {
		LPC_ICH = 0, /* ICH */
		@@ -216,6 +242,7 @@ enum lpc_chipsets {
		LPC_BRASWELL, /* Braswell SoC */
		LPC_LEWISBURG, /* Lewisburg */
		LPC_9S, /* 9 Series */
		LPC_APL, /* Apollo Lake SoC */
		};

		static struct lpc_ich_info lpc_chipset_info[] = {
		@@ -494,10 +521,12 @@ static struct lpc_ich_info lpc_chipset_info[] = {
		.name = "Lynx Point",
		.iTCO_version = 2,
		.gpio_version = ICH_V5_GPIO,
		.spi_type = INTEL_SPI_LPT,
		},
		[LPC_LPT_LP] = {
		.name = "Lynx Point_LP",
		.iTCO_version = 2,
		.spi_type = INTEL_SPI_LPT,
		},
		[LPC_WBG] = {
		.name = "Wellsburg",
		@@ -511,6 +540,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
		[LPC_BAYTRAIL] = {
		.name = "Bay Trail SoC",
		.iTCO_version = 3,
		.spi_type = INTEL_SPI_BYT,
		},
		[LPC_COLETO] = {
		.name = "Coleto Creek",
		@@ -519,10 +549,12 @@ static struct lpc_ich_info lpc_chipset_info[] = {
		[LPC_WPT_LP] = {
		.name = "Wildcat Point_LP",
		.iTCO_version = 2,
		.spi_type = INTEL_SPI_LPT,
		},
		[LPC_BRASWELL] = {
		.name = "Braswell SoC",
		.iTCO_version = 3,
		.spi_type = INTEL_SPI_BYT,
		},
		[LPC_LEWISBURG] = {
		.name = "Lewisburg",
		@@ -533,6 +565,10 @@ static struct lpc_ich_info lpc_chipset_info[] = {
		.iTCO_version = 2,
		.gpio_version = ICH_V5_GPIO,
		},
		[LPC_APL] = {
		.name = "Apollo Lake SoC",
		.spi_type = INTEL_SPI_BXT,
		},
		};

		/*
		@@ -681,6 +717,7 @@ static const struct pci_device_id lpc_ich_ids[] = {
		{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
		{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
		{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
		{ PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
		{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
		{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
		{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
		@@ -1056,6 +1093,94 @@ static int lpc_ich_init_wdt(struct pci_dev *dev)
		return ret;
		}

		static int lpc_ich_init_spi(struct pci_dev *dev)
		{
		struct lpc_ich_priv *priv = pci_get_drvdata(dev);
		struct resource *res = &intel_spi_res[0];
		struct intel_spi_boardinfo *info;
		u32 spi_base, rcba, bcr;

		info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
		if (!info)
		return -ENOMEM;

		info->type = lpc_chipset_info[priv->chipset].spi_type;

		switch (info->type) {
		case INTEL_SPI_BYT:
		pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
		if (spi_base & SPIBASE_BYT_EN) {
		res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
		res->end = res->start + SPIBASE_BYT_SZ - 1;
		}
		break;

		case INTEL_SPI_LPT:
		pci_read_config_dword(dev, RCBABASE, &rcba);
		if (rcba & 1) {
		spi_base = round_down(rcba, SPIBASE_LPT_SZ);
		res->start = spi_base + SPIBASE_LPT;
		res->end = res->start + SPIBASE_LPT_SZ - 1;

		/*
		* Try to make the flash chip writeable now by
		* setting BCR_WPD. It it fails we tell the driver
		* that it can only read the chip.
		*/
		pci_read_config_dword(dev, BCR, &bcr);
		if (!(bcr & BCR_WPD)) {
		bcr \|= BCR_WPD;
		pci_write_config_dword(dev, BCR, bcr);
		pci_read_config_dword(dev, BCR, &bcr);
		}
		info->writeable = !!(bcr & BCR_WPD);
		}
		break;

		case INTEL_SPI_BXT: {
		unsigned int p2sb = PCI_DEVFN(13, 0);
		unsigned int spi = PCI_DEVFN(13, 2);
		struct pci_bus *bus = dev->bus;

		/*
		* The P2SB is hidden by BIOS and we need to unhide it in
		* order to read BAR of the SPI flash device. Once that is
		* done we hide it again.
		*/
		pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
		pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
		&spi_base);
		if (spi_base != ~0) {
		res->start = spi_base & 0xfffffff0;
		res->end = res->start + SPIBASE_APL_SZ - 1;

		pci_bus_read_config_dword(bus, spi, BCR, &bcr);
		if (!(bcr & BCR_WPD)) {
		bcr \|= BCR_WPD;
		pci_bus_write_config_dword(bus, spi, BCR, bcr);
		pci_bus_read_config_dword(bus, spi, BCR, &bcr);
		}
		info->writeable = !!(bcr & BCR_WPD);
		}

		pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
		break;
		}

		default:
		return -EINVAL;
		}

		if (!res->start)
		return -ENODEV;

		lpc_ich_spi_cell.platform_data = info;
		lpc_ich_spi_cell.pdata_size = sizeof(*info);

		return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
		&lpc_ich_spi_cell, 1, NULL, 0, NULL);
		}

		static int lpc_ich_probe(struct pci_dev *dev,
		const struct pci_device_id *id)
		{
		@@ -1099,6 +1224,12 @@ static int lpc_ich_probe(struct pci_dev *dev,
		cell_added = true;
		}

		if (lpc_chipset_info[priv->chipset].spi_type) {
		ret = lpc_ich_init_spi(dev);
		if (!ret)
		cell_added = true;
		}

		/*
		* We only care if at least one or none of the cells registered
		* successfully.

drivers/mtd/spi-nor/Kconfig

+20 −0

Original line number	Diff line number	Diff line
		@@ -86,4 +86,24 @@ config SPI_NXP_SPIFI
		Flash. Enable this option if you have a device with a SPIFI
		controller and want to access the Flash as a mtd device.

		config SPI_INTEL_SPI
		tristate

		config SPI_INTEL_SPI_PLATFORM
		tristate "Intel PCH/PCU SPI flash platform driver" if EXPERT
		depends on X86
		select SPI_INTEL_SPI
		help
		This enables platform support for the Intel PCH/PCU SPI
		controller in master mode. This controller is present in modern
		Intel hardware and is used to hold BIOS and other persistent
		settings. Using this driver it is possible to upgrade BIOS
		directly from Linux.

		Say N here unless you know what you are doing. Overwriting the
		SPI flash may render the system unbootable.

		To compile this driver as a module, choose M here: the module
		will be called intel-spi-platform.

		endif # MTD_SPI_NOR

drivers/mtd/spi-nor/Makefile

+2 −0

Original line number	Diff line number	Diff line
		@@ -6,3 +6,5 @@ obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
		obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
		obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
		obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
		obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
		obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o

drivers/mtd/spi-nor/intel-spi-platform.c

0 → 100644

+57 −0

Original line number	Diff line number	Diff line
		/*
		* Intel PCH/PCU SPI flash platform driver.
		*
		* Copyright (C) 2016, Intel Corporation
		* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*/

		#include <linux/ioport.h>
		#include <linux/module.h>
		#include <linux/platform_device.h>

		#include "intel-spi.h"

		static int intel_spi_platform_probe(struct platform_device *pdev)
		{
		struct intel_spi_boardinfo *info;
		struct intel_spi *ispi;
		struct resource *mem;

		info = dev_get_platdata(&pdev->dev);
		if (!info)
		return -EINVAL;

		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		ispi = intel_spi_probe(&pdev->dev, mem, info);
		if (IS_ERR(ispi))
		return PTR_ERR(ispi);

		platform_set_drvdata(pdev, ispi);
		return 0;
		}

		static int intel_spi_platform_remove(struct platform_device *pdev)
		{
		struct intel_spi *ispi = platform_get_drvdata(pdev);

		return intel_spi_remove(ispi);
		}

		static struct platform_driver intel_spi_platform_driver = {
		.probe = intel_spi_platform_probe,
		.remove = intel_spi_platform_remove,
		.driver = {
		.name = "intel-spi",
		},
		};

		module_platform_driver(intel_spi_platform_driver);

		MODULE_DESCRIPTION("Intel PCH/PCU SPI flash platform driver");
		MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
		MODULE_LICENSE("GPL v2");
		MODULE_ALIAS("platform:intel-spi");