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Commit 9d495a97 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable PSCI enable method for the CPUs" into msm-next

parents 99ab5cd7 758fc6c7

arch/arm64/boot/dts/qcom/sdm855.dtsi

+13 −16
Original line number Diff line number Diff line
@@ -36,9 +36,8 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "spin-table";

			enable-method = "psci";

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -58,9 +57,8 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "spin-table";

			enable-method = "psci";

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";
@@ -74,9 +72,8 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "spin-table";

			enable-method = "psci";

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";
@@ -90,9 +87,8 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "spin-table";

			enable-method = "psci";

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_3>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";
@@ -106,9 +102,8 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "spin-table";

			enable-method = "psci";

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_4>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";
@@ -122,9 +117,8 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "spin-table";

			enable-method = "psci";

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_5>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";
@@ -138,9 +132,8 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "spin-table";

			enable-method = "psci";

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_6>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";
@@ -154,9 +147,8 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "spin-table";

			enable-method = "psci";

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_7>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";
@@ -205,6 +197,11 @@ 
		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	soc: soc { };



	reserved-memory {