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Commit 9d196dea authored by Zhiqiang Tu's avatar Zhiqiang Tu
Browse files

clk: qcom: Add usb and pcie virtio clocks for sa8195p 



Add clocks required by usb and pcie pass-through on sa8195p
virtual machine.

Change-Id: Ibeddc2b97f6365766797310601a12336380ab2a6
Signed-off-by: default avatarZhiqiang Tu <ztu@codeaurora.org>
parent 5431ddf1

drivers/clk/qcom/virtio_clk_sa8195p.c

+17 −0
Original line number Diff line number Diff line
@@ -45,11 +45,26 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { 
	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = "gcc_cfg_noc_usb3_prim_axi_clk",

	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = "gcc_aggre_usb3_prim_axi_clk",

	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = "gcc_usb30_prim_mock_utmi_clk",

	[GCC_USB30_PRIM_SLEEP_CLK] = "gcc_usb30_prim_sleep_clk",

	[GCC_USB3_PRIM_PHY_AUX_CLK] = "gcc_usb3_prim_phy_aux_clk",

	[GCC_USB3_PRIM_PHY_PIPE_CLK] = "gcc_usb3_prim_phy_pipe_clk",

	[GCC_USB3_PRIM_CLKREF_CLK] = "gcc_usb3_prim_clkref_en",

	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = "gcc_usb3_prim_phy_com_aux_clk",

	[GCC_USB30_SEC_MASTER_CLK] = "gcc_usb30_sec_master_clk",

	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = "gcc_cfg_noc_usb3_sec_axi_clk",

	[GCC_AGGRE_USB3_SEC_AXI_CLK] = "gcc_aggre_usb3_sec_axi_clk",

	[GCC_USB30_SEC_MOCK_UTMI_CLK] = "gcc_usb30_sec_mock_utmi_clk",

	[GCC_USB30_SEC_SLEEP_CLK] = "gcc_usb30_sec_sleep_clk",

	[GCC_USB3_SEC_PHY_AUX_CLK] = "gcc_usb3_sec_phy_aux_clk",

	[GCC_USB3_SEC_PHY_PIPE_CLK] = "gcc_usb3_sec_phy_pipe_clk",

	[GCC_USB3_SEC_CLKREF_CLK] = "gcc_usb3_sec_clkref_en",

	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = "gcc_usb3_sec_phy_com_aux_clk",

	[GCC_PCIE_0_PIPE_CLK] = "gcc_pcie_0_pipe_clk",

	[GCC_PCIE_0_AUX_CLK] = "gcc_pcie_0_aux_clk",

	[GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk",

	[GCC_PCIE_0_MSTR_AXI_CLK] = "gcc_pcie_0_mstr_axi_clk",

	[GCC_PCIE_0_SLV_AXI_CLK] = "gcc_pcie_0_slv_axi_clk",

	[GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_en",

	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = "gcc_pcie_0_slv_q2a_axi_clk",

	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = "gcc_aggre_noc_pcie_tbu_clk",

	[GCC_PCIE0_PHY_REFGEN_CLK] = "gcc_pcie0_phy_refgen_clk",
@@ -60,7 +75,9 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { 


static const char * const sa8195p_gcc_virtio_resets[] = {

	[GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr",

	[GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr",

	[GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk",

	[GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk",

	[GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk",

	[GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr",

};