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Commit 9d0f8140 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming 

Pull C6X atomic64 support from Mark Salter:
 "Enable atomic64 ops in C6X
   - define L1_CACHE_SHIFT
   - select GENERIC_ATOMIC64"

* tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming:
  C6X: select GENERIC_ATOMIC64
  C6X: add Lx_CACHE_SHIFT defines
parents ef824bfb 01ddd9a8

arch/c6x/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
config C6X

	def_bool y

	select CLKDEV_LOOKUP

	select GENERIC_ATOMIC64

	select GENERIC_IRQ_SHOW

	select HAVE_ARCH_TRACEHOOK

	select HAVE_DMA_API_DEBUG

arch/c6x/include/asm/cache.h

+11 −5
Original line number Diff line number Diff line 
/*

 *  Port on Texas Instruments TMS320C6x architecture

 *

 *  Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated

 *  Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated

 *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)

 *

 *  This program is free software; you can redistribute it and/or modify
@@ -16,9 +16,14 @@ 
/*

 * Cache line size

 */

#define L1D_CACHE_BYTES   64

#define L1P_CACHE_BYTES   32

#define L2_CACHE_BYTES	  128

#define L1D_CACHE_SHIFT   6

#define L1D_CACHE_BYTES   (1 << L1D_CACHE_SHIFT)



#define L1P_CACHE_SHIFT   5

#define L1P_CACHE_BYTES   (1 << L1P_CACHE_SHIFT)



#define L2_CACHE_SHIFT    7

#define L2_CACHE_BYTES    (1 << L2_CACHE_SHIFT)



/*

 * L2 used as cache
@@ -29,7 +34,8 @@ 
 * For practical reasons the L1_CACHE_BYTES defines should not be smaller than

 * the L2 line size

 */

#define L1_CACHE_BYTES        L2_CACHE_BYTES

#define L1_CACHE_SHIFT        L2_CACHE_SHIFT

#define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)



#define L2_CACHE_ALIGN_LOW(x) \

	(((x) & ~(L2_CACHE_BYTES - 1)))