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Commit 9c5bbad4 authored by Shubhashree Dhar's avatar Shubhashree Dhar
Browse files

drm/msm/sde: add qdss support for display driver 



Add support for qdss in display driver to enable tracking
of the mdp hardware events.

Change-Id: I7b2aaf8eec9c8d4641e17689a2833638df8ee849
Signed-off-by: default avatarShubhashree Dhar <dhar@codeaurora.org>
parent c7417c17

Documentation/devicetree/bindings/display/msm/sde.txt

+1 −0
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ Optional properties: 
- qcom,sde-te-size:		A u32 value indicates the te block address range.

- qcom,sde-te2-size:		A u32 value indicates the te2 block address range.

- qcom,sde-dsc-off:	 	A u32 offset indicates the dsc block offset on pingpong.

- qcom,sde-qdss-off:		A u32 offset indicates the qdss block offset.

- qcom,sde-dither-off:		A u32 offset indicates the dither block offset on pingpong.

- qcom,sde-dither-version:	A u32 value indicates the dither block version.

- qcom,sde-dither-size:		A u32 value indicates the dither block address range.

drivers/gpu/drm/msm/sde/sde_encoder.c

+42 −1
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ 
#include "sde_crtc.h"

#include "sde_trace.h"

#include "sde_core_irq.h"

#include "sde_hw_top.h"

#include "sde_hw_qdss.h"



#define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\

		(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
@@ -180,6 +182,7 @@ enum sde_enc_rc_states { 
 * @intfs_swapped	Whether or not the phys_enc interfaces have been swapped

 *			for partial update right-only cases, such as pingpong

 *			split where virtual pingpong does not generate IRQs

 * @qdss_status:		indicate if qdss is modified since last update

 * @crtc_vblank_cb:	Callback into the upper layer / CRTC for

 *			notification of the VBLANK

 * @crtc_vblank_cb_data:	Data from upper layer for VBLANK notification
@@ -243,6 +246,7 @@ struct sde_encoder_virt { 
	enum sde_dsc dirty_dsc_ids[MAX_CHANNELS_PER_ENC];



	bool intfs_swapped;

	bool qdss_status;



	void (*crtc_vblank_cb)(void *);

	void *crtc_vblank_cb_data;
@@ -388,6 +392,20 @@ static bool _sde_encoder_is_dsc_enabled(struct drm_encoder *drm_enc) 
	return (comp_info->comp_type == MSM_DISPLAY_COMPRESSION_DSC);

}



static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,

				struct sde_hw_qdss *hw_qdss,

				struct sde_encoder_phys *phys, bool enable)

{

	if (sde_enc->qdss_status == enable)

		return;



	sde_enc->qdss_status = enable;



	phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,

						sde_enc->qdss_status);

	hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);

}



static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,

	s64 timeout_ms, struct sde_encoder_wait_info *info)

{
@@ -2675,7 +2693,7 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc, 
	struct drm_connector *conn = NULL, *conn_iter;

	struct sde_connector_state *sde_conn_state = NULL;

	struct sde_connector *sde_conn = NULL;

	struct sde_rm_hw_iter dsc_iter, pp_iter;

	struct sde_rm_hw_iter dsc_iter, pp_iter, qdss_iter;

	struct sde_rm_hw_request request_hw;

	bool is_cmd_mode = false;

	int i = 0, ret;
@@ -2775,6 +2793,22 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc, 
		sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;

	}



	for (i = 0; i < sde_enc->num_phys_encs; i++) {

		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];



		if (phys) {

			sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,

						SDE_HW_BLK_QDSS);

			for (i = 0; i < QDSS_MAX; i++) {

				if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {

					phys->hw_qdss =

					(struct sde_hw_qdss *)qdss_iter.hw;

					break;

				}

			}

		}

	}



	sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);

	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {

		sde_enc->hw_dsc[i] = NULL;
@@ -4453,6 +4487,7 @@ int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, 
	struct sde_encoder_virt *sde_enc;

	struct sde_encoder_phys *phys;

	struct sde_kms *sde_kms = NULL;

	struct sde_crtc *sde_crtc;

	struct msm_drm_private *priv = NULL;

	bool needs_hw_reset = false;

	uint32_t ln_cnt1, ln_cnt2;
@@ -4469,6 +4504,7 @@ int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, 
	priv = drm_enc->dev->dev_private;

	sde_kms = to_sde_kms(priv->kms);

	disp_info = &sde_enc->disp_info;

	sde_crtc = to_sde_crtc(sde_enc->crtc);



	SDE_DEBUG_ENC(sde_enc, "\n");

	SDE_EVT32(DRMID(drm_enc));
@@ -4560,6 +4596,10 @@ int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, 
		_helper_flush_dsc(sde_enc);

	}



	if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)

		sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,

				sde_enc->cur_master, sde_kms->qdss_enabled);



end:

	SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");

	return ret;
@@ -5278,6 +5318,7 @@ struct drm_encoder *sde_encoder_init_with_ops( 
	kthread_init_delayed_work(&sde_enc->delayed_off_work,

			sde_encoder_off_work);

	sde_enc->vblank_enabled = false;

	sde_enc->qdss_status = false;



	kthread_init_work(&sde_enc->vsync_event_work,

			sde_encoder_vsync_event_work_handler);

drivers/gpu/drm/msm/sde/sde_encoder_phys.h

+2 −0
Original line number Diff line number Diff line
@@ -256,6 +256,7 @@ struct sde_encoder_irq { 
 * @hw_ctl:		Hardware interface to the ctl registers

 * @hw_intf:		Hardware interface to INTF registers

 * @hw_cdm:		Hardware interface to the cdm registers

 * @hw_qdss:		Hardware interface to the qdss registers

 * @cdm_cfg:		Chroma-down hardware configuration

 * @hw_pp:		Hardware interface to the ping pong registers

 * @sde_kms:		Pointer to the sde_kms top level
@@ -305,6 +306,7 @@ struct sde_encoder_phys { 
	struct sde_hw_ctl *hw_ctl;

	struct sde_hw_intf *hw_intf;

	struct sde_hw_cdm *hw_cdm;

	struct sde_hw_qdss *hw_qdss;

	struct sde_hw_cdm_cfg cdm_cfg;

	struct sde_hw_pingpong *hw_pp;

	struct sde_kms *sde_kms;

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+2 −1
Original line number Diff line number Diff line
@@ -3477,7 +3477,8 @@ static int sde_parse_merge_3d_dt(struct device_node *np, 
	return rc;

}



int sde_qdss_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)

static int sde_qdss_parse_dt(struct device_node *np,

				struct sde_mdss_cfg *sde_cfg)

{

	int rc, prop_count[HW_PROP_MAX], i;

	struct sde_prop_value *prop_value = NULL;

drivers/gpu/drm/msm/sde/sde_hw_top.c

+13 −0
Original line number Diff line number Diff line
@@ -419,6 +419,18 @@ static void sde_hw_intf_audio_select(struct sde_hw_mdp *mdp) 
	SDE_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);

}



static void sde_hw_mdp_events(struct sde_hw_mdp *mdp, bool enable)

{

	struct sde_hw_blk_reg_map *c;



	if (!mdp)

		return;



	c = &mdp->hw;



	SDE_REG_WRITE(c, HW_EVENTS_CTL, enable);

}



static void sde_hw_program_cwb_ppb_ctrl(struct sde_hw_mdp *mdp,

		bool dual, bool dspp_out)

{
@@ -446,6 +458,7 @@ static void _setup_mdp_ops(struct sde_hw_mdp_ops *ops, 
	ops->setup_dce = sde_hw_setup_dce;

	ops->reset_ubwc = sde_hw_reset_ubwc;

	ops->intf_audio_select = sde_hw_intf_audio_select;

	ops->set_mdp_hw_events = sde_hw_mdp_events;

	if (cap & BIT(SDE_MDP_VSYNC_SEL))

		ops->setup_vsync_source = sde_hw_setup_vsync_source;

	else