Merge "clk: smd-rpm: Add support for additional clocks for QCS405" (9c57956a) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/clk-smd-rpm.c

+7 −4

Original line number	Diff line number	Diff line
		@@ -610,9 +610,10 @@ DEFINE_CLK_SMD_RPM(qcs405, bimc_gpu_clk, bimc_gpu_a_clk,
		/* SMD_XO_BUFFER */
		DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, ln_bb_clk, ln_bb_clk_a, 8);
		DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk1, rf_clk1_a, 4);
		DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, div_clk1, div_clk1_a, 0xb);
		DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk3, rf_clk3_a, 6);
		DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, ln_bb_clk_pin, ln_bb_clk_a_pin, 8);
		DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, rf_clk1_pin, rf_clk1_a_pin, 4);
		DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, rf_clk3_pin, rf_clk3_a_pin, 6);

		/* Voter clocks */
		static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX);
		@@ -663,12 +664,14 @@ static struct clk_hw *qcs405_clks[] = {
		[RPM_SMD_RF_CLK1_A] = &qcs405_rf_clk1_a.hw,
		[RPM_SMD_RF_CLK1_PIN] = &qcs405_rf_clk1_pin.hw,
		[RPM_SMD_RF_CLK1_A_PIN] = &qcs405_rf_clk1_a_pin.hw,
		[RPM_SMD_RF_CLK3] = &qcs405_rf_clk3.hw,
		[RPM_SMD_RF_CLK3_A] = &qcs405_rf_clk3_a.hw,
		[RPM_SMD_RF_CLK3_PIN] = &qcs405_rf_clk3_pin.hw,
		[RPM_SMD_RF_CLK3_A_PIN] = &qcs405_rf_clk3_a_pin.hw,
		[RPM_SMD_LN_BB_CLK] = &qcs405_ln_bb_clk.hw,
		[RPM_SMD_LN_BB_CLK_A] = &qcs405_ln_bb_clk_a.hw,
		[RPM_SMD_LN_BB_CLK_PIN] = &qcs405_ln_bb_clk_pin.hw,
		[RPM_SMD_LN_BB_CLK_A_PIN] = &qcs405_ln_bb_clk_a_pin.hw,
		[RPM_SMD_DIV_CLK1] = &qcs405_div_clk1.hw,
		[RPM_SMD_DIV_A_CLK1] = &qcs405_div_clk1_a.hw,
		[RPM_SMD_PNOC_CLK] = &qcs405_pnoc_clk.hw,
		[RPM_SMD_PNOC_A_CLK] = &qcs405_pnoc_a_clk.hw,
		[RPM_SMD_CE1_CLK] = &qcs405_ce1_clk.hw,
		@@ -708,7 +711,7 @@ static struct clk_hw *qcs405_clks[] = {

		static const struct rpm_smd_clk_desc rpm_clk_qcs405 = {
		.clks = qcs405_clks,
		.num_rpm_clks = RPM_SMD_BIMC_GPU_A_CLK,
		.num_rpm_clks = RPM_SMD_RF_CLK3_A_PIN,
		.num_clks = ARRAY_SIZE(qcs405_clks),
		};

include/dt-bindings/clock/qcom,rpmcc.h

+31 −27

Original line number	Diff line number	Diff line
		@@ -111,32 +111,36 @@
		#define RPM_SMD_LN_BB_CLK_A 71
		#define RPM_SMD_LN_BB_CLK_PIN 72
		#define RPM_SMD_LN_BB_CLK_A_PIN 73
		#define PNOC_MSMBUS_CLK 74
		#define PNOC_MSMBUS_A_CLK 75
		#define PNOC_KEEPALIVE_A_CLK 76
		#define SNOC_MSMBUS_CLK 77
		#define SNOC_MSMBUS_A_CLK 78
		#define BIMC_MSMBUS_CLK 79
		#define BIMC_MSMBUS_A_CLK 80
		#define PNOC_USB_CLK 81
		#define PNOC_USB_A_CLK 82
		#define SNOC_USB_CLK 83
		#define SNOC_USB_A_CLK 84
		#define BIMC_USB_CLK 85
		#define BIMC_USB_A_CLK 86
		#define SNOC_WCNSS_A_CLK 87
		#define BIMC_WCNSS_A_CLK 88
		#define MCD_CE1_CLK 89
		#define QCEDEV_CE1_CLK 90
		#define QCRYPTO_CE1_CLK 91
		#define QSEECOM_CE1_CLK 92
		#define SCM_CE1_CLK 93
		#define CXO_SMD_OTG_CLK 94
		#define CXO_SMD_LPM_CLK 95
		#define CXO_SMD_PIL_PRONTO_CLK 96
		#define CXO_SMD_PIL_MSS_CLK 97
		#define CXO_SMD_WLAN_CLK 98
		#define CXO_SMD_PIL_LPASS_CLK 99
		#define CXO_SMD_PIL_CDSP_CLK 100
		#define RPM_SMD_RF_CLK3 74
		#define RPM_SMD_RF_CLK3_A 75
		#define RPM_SMD_RF_CLK3_PIN 76
		#define RPM_SMD_RF_CLK3_A_PIN 77
		#define PNOC_MSMBUS_CLK 78
		#define PNOC_MSMBUS_A_CLK 79
		#define PNOC_KEEPALIVE_A_CLK 80
		#define SNOC_MSMBUS_CLK 81
		#define SNOC_MSMBUS_A_CLK 82
		#define BIMC_MSMBUS_CLK 83
		#define BIMC_MSMBUS_A_CLK 84
		#define PNOC_USB_CLK 85
		#define PNOC_USB_A_CLK 86
		#define SNOC_USB_CLK 87
		#define SNOC_USB_A_CLK 88
		#define BIMC_USB_CLK 89
		#define BIMC_USB_A_CLK 90
		#define SNOC_WCNSS_A_CLK 91
		#define BIMC_WCNSS_A_CLK 92
		#define MCD_CE1_CLK 93
		#define QCEDEV_CE1_CLK 94
		#define QCRYPTO_CE1_CLK 95
		#define QSEECOM_CE1_CLK 96
		#define SCM_CE1_CLK 97
		#define CXO_SMD_OTG_CLK 98
		#define CXO_SMD_LPM_CLK 99
		#define CXO_SMD_PIL_PRONTO_CLK 100
		#define CXO_SMD_PIL_MSS_CLK 101
		#define CXO_SMD_WLAN_CLK 102
		#define CXO_SMD_PIL_LPASS_CLK 103
		#define CXO_SMD_PIL_CDSP_CLK 104

		#endif