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Commit 9c5753bc authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/disp/nv50-: port OR power state control to nvkm_ior 



Also removes the user-facing methods to these controls, as they're not
currently utilised by the DD anyway.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 29c0ca73

drivers/gpu/drm/nouveau/include/nvif/cl5070.h

+0 −25
Original line number Diff line number Diff line
@@ -27,30 +27,18 @@ struct nv50_disp_scanoutpos_v0 { 


struct nv50_disp_mthd_v1 {

	__u8  version;

#define NV50_DISP_MTHD_V1_DAC_PWR                                          0x10

#define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11

#define NV50_DISP_MTHD_V1_SOR_PWR                                          0x20

#define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21

#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22

#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23

#define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK                                  0x25

#define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI                                  0x26

#define NV50_DISP_MTHD_V1_PIOR_PWR                                         0x30

	__u8  method;

	__u16 hasht;

	__u16 hashm;

	__u8  pad06[2];

};



struct nv50_disp_dac_pwr_v0 {

	__u8  version;

	__u8  state;

	__u8  data;

	__u8  vsync;

	__u8  hsync;

	__u8  pad05[3];

};



struct nv50_disp_dac_load_v0 {

	__u8  version;

	__u8  load;
@@ -58,12 +46,6 @@ struct nv50_disp_dac_load_v0 { 
	__u32 data;

};



struct nv50_disp_sor_pwr_v0 {

	__u8  version;

	__u8  state;

	__u8  pad02[6];

};



struct nv50_disp_sor_hda_eld_v0 {

	__u8  version;

	__u8  pad01[7];
@@ -101,11 +83,4 @@ struct nv50_disp_sor_dp_mst_vcpi_v0 { 
	__u16 pbn;

	__u16 aligned_pbn;

};



struct nv50_disp_pior_pwr_v0 {

	__u8  version;

	__u8  state;

	__u8  type;

	__u8  pad03[5];

};

#endif

drivers/gpu/drm/nouveau/nv50_display.c

+2 −74
Original line number Diff line number Diff line
@@ -2459,30 +2459,6 @@ nv50_outp_atomic_check(struct drm_encoder *encoder, 
/******************************************************************************

 * DAC

 *****************************************************************************/

static void

nv50_dac_dpms(struct drm_encoder *encoder, int mode)

{

	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);

	struct nv50_disp *disp = nv50_disp(encoder->dev);

	struct {

		struct nv50_disp_mthd_v1 base;

		struct nv50_disp_dac_pwr_v0 pwr;

	} args = {

		.base.version = 1,

		.base.method = NV50_DISP_MTHD_V1_DAC_PWR,

		.base.hasht  = nv_encoder->dcb->hasht,

		.base.hashm  = nv_encoder->dcb->hashm,

		.pwr.state = 1,

		.pwr.data  = 1,

		.pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&

			      mode != DRM_MODE_DPMS_OFF),

		.pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&

			      mode != DRM_MODE_DPMS_OFF),

	};



	nvif_mthd(disp->disp, 0, &args, sizeof(args));

}



static void

nv50_dac_disable(struct drm_encoder *encoder)

{
@@ -2584,7 +2560,6 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 


static const struct drm_encoder_helper_funcs

nv50_dac_help = {

	.dpms = nv50_dac_dpms,

	.atomic_check = nv50_outp_atomic_check,

	.enable = nv50_dac_enable,

	.disable = nv50_dac_disable,
@@ -3405,25 +3380,6 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 
/******************************************************************************

 * SOR

 *****************************************************************************/

static void

nv50_sor_dpms(struct drm_encoder *encoder, int mode)

{

	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);

	struct nv50_disp *disp = nv50_disp(encoder->dev);

	struct {

		struct nv50_disp_mthd_v1 base;

		struct nv50_disp_sor_pwr_v0 pwr;

	} args = {

		.base.version = 1,

		.base.method = NV50_DISP_MTHD_V1_SOR_PWR,

		.base.hasht  = nv_encoder->dcb->hasht,

		.base.hashm  = nv_encoder->dcb->hashm,

		.pwr.state = mode == DRM_MODE_DPMS_ON,

	};



	nvif_mthd(disp->disp, 0, &args, sizeof(args));

}



static void

nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,

		struct drm_display_mode *mode, u8 proto, u8 depth)
@@ -3602,7 +3558,6 @@ nv50_sor_enable(struct drm_encoder *encoder) 


static const struct drm_encoder_helper_funcs

nv50_sor_help = {

	.dpms = nv50_sor_dpms,

	.atomic_check = nv50_outp_atomic_check,

	.enable = nv50_sor_enable,

	.disable = nv50_sor_disable,
@@ -3686,26 +3641,6 @@ nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 
/******************************************************************************

 * PIOR

 *****************************************************************************/

static void

nv50_pior_dpms(struct drm_encoder *encoder, int mode)

{

	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);

	struct nv50_disp *disp = nv50_disp(encoder->dev);

	struct {

		struct nv50_disp_mthd_v1 base;

		struct nv50_disp_pior_pwr_v0 pwr;

	} args = {

		.base.version = 1,

		.base.method = NV50_DISP_MTHD_V1_PIOR_PWR,

		.base.hasht  = nv_encoder->dcb->hasht,

		.base.hashm  = nv_encoder->dcb->hashm,

		.pwr.state = mode == DRM_MODE_DPMS_ON,

		.pwr.type = nv_encoder->dcb->type,

	};



	nvif_mthd(disp->disp, 0, &args, sizeof(args));

}



static int

nv50_pior_atomic_check(struct drm_encoder *encoder,

		       struct drm_crtc_state *crtc_state,
@@ -3790,7 +3725,6 @@ nv50_pior_enable(struct drm_encoder *encoder) 


static const struct drm_encoder_helper_funcs

nv50_pior_help = {

	.dpms = nv50_pior_dpms,

	.atomic_check = nv50_pior_atomic_check,

	.enable = nv50_pior_enable,

	.disable = nv50_pior_disable,
@@ -4355,14 +4289,8 @@ nv50_display_init(struct drm_device *dev) 


	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

		if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {

			const struct drm_encoder_helper_funcs *help;

			struct nouveau_encoder *nv_encoder;



			nv_encoder = nouveau_encoder(encoder);

			help = encoder->helper_private;

			if (help && help->dpms)

				help->dpms(encoder, DRM_MODE_DPMS_ON);



			struct nouveau_encoder *nv_encoder =

				nouveau_encoder(encoder);

			nv50_mstm_init(nv_encoder->dp.mstm);

		}

	}

drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ gf119_dac_state(struct nvkm_ior *dac, struct nvkm_ior_state *state) 
static const struct nvkm_ior_func

gf119_dac = {

	.state = gf119_dac_state,

	.power = nv50_dac_power,

};



int

drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c

+21 −29
Original line number Diff line number Diff line
@@ -90,40 +90,31 @@ nv50_dac_sense(NV50_DISP_MTHD_V1) 
	return 0;

}



int

nv50_dac_power(NV50_DISP_MTHD_V1)

static void

nv50_dac_power_wait(struct nvkm_device *device, const u32 doff)

{

	struct nvkm_device *device = disp->base.engine.subdev.device;

	const u32 doff = outp->or * 0x800;

	union {

		struct nv50_disp_dac_pwr_v0 v0;

	} *args = data;

	u32 stat;

	int ret = -ENOSYS;



	nvif_ioctl(object, "disp dac pwr size %d\n", size);

	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

		nvif_ioctl(object, "disp dac pwr vers %d state %d data %d "

				   "vsync %d hsync %d\n",

			   args->v0.version, args->v0.state, args->v0.data,

			   args->v0.vsync, args->v0.hsync);

		stat  = 0x00000040 * !args->v0.state;

		stat |= 0x00000010 * !args->v0.data;

		stat |= 0x00000004 * !args->v0.vsync;

		stat |= 0x00000001 * !args->v0.hsync;

	} else

		return ret;



	nvkm_msec(device, 2000,

		if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000))

			break;

	);

	nvkm_mask(device, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);

	nvkm_msec(device, 2000,

		if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000))

			break;

	);

	return 0;

}



void

nv50_dac_power(struct nvkm_ior *dac, bool normal, bool pu,

	       bool data, bool vsync, bool hsync)

{

	struct nvkm_device *device = dac->disp->engine.subdev.device;

	const u32  doff = nv50_ior_base(dac);

	const u32 shift = normal ? 0 : 16;

	const u32 state = 0x80000000 | (0x00000040 * !    pu |

					0x00000010 * !  data |

					0x00000004 * ! vsync |

					0x00000001 * ! hsync) << shift;

	const u32 field = 0xc0000000 | (0x00000055 << shift);



	nv50_dac_power_wait(device, doff);

	nvkm_mask(device, 0x61a004 + doff, field, state);

	nv50_dac_power_wait(device, doff);

}



static void
@@ -147,6 +138,7 @@ nv50_dac_state(struct nvkm_ior *dac, struct nvkm_ior_state *state) 
static const struct nvkm_ior_func

nv50_dac = {

	.state = nv50_dac_state,

	.power = nv50_dac_power,

};



int

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

+1 −5
Original line number Diff line number Diff line
@@ -40,15 +40,11 @@ g84_disp = { 
	.outp.external.dp = nv50_pior_dp_new,

	.dac.nr = 3,

	.dac.new = nv50_dac_new,

	.dac.power = nv50_dac_power,

	.dac.sense = nv50_dac_sense,

	.sor.nr = 2,

	.sor.new = g84_sor_new,

	.sor.power = nv50_sor_power,

	.sor.hdmi = g84_hdmi_ctrl,

	.pior.nr = 3,

	.pior.new = nv50_pior_new,

	.pior.power = nv50_pior_power,

	.pior = { .nr = 3, .new = nv50_pior_new },

};



int