Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9bc297ea authored by Nithin Sujir's avatar Nithin Sujir Committed by David S. Miller
Browse files

tg3: Add read dma workaround for 5720 



Commit 091f0ea3 "tg3: Add New 5719 Read
DMA workaround" added a workaround for TX DMA stall on the 5719. This
workaround needs to be applied to the 5720 as well.

Cc: stable@vger.kernel.org
Reported-by: default avatarRoland Dreier <roland@purestorage.com>
Tested-by: default avatarRoland Dreier <roland@purestorage.com>
Signed-off-by: default avatarNithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3a5395b3

drivers/net/ethernet/broadcom/tg3.c

+15 −6
Original line number Diff line number Diff line
@@ -9468,6 +9468,14 @@ static void tg3_rss_write_indir_tbl(struct tg3 *tp) 
	}

}



static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)

{

	if (tg3_asic_rev(tp) == ASIC_REV_5719)

		return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;

	else

		return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;

}



/* tp->lock is held. */

static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)

{
@@ -10153,16 +10161,17 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) 
	tw32_f(RDMAC_MODE, rdmac_mode);

	udelay(40);



	if (tg3_asic_rev(tp) == ASIC_REV_5719) {

	if (tg3_asic_rev(tp) == ASIC_REV_5719 ||

	    tg3_asic_rev(tp) == ASIC_REV_5720) {

		for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {

			if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))

				break;

		}

		if (i < TG3_NUM_RDMA_CHANNELS) {

			val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);

			val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;

			val |= tg3_lso_rd_dma_workaround_bit(tp);

			tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);

			tg3_flag_set(tp, 5719_RDMA_BUG);

			tg3_flag_set(tp, 5719_5720_RDMA_BUG);

		}

	}
@@ -10526,15 +10535,15 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp) 
	TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);

	TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);

	TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);

	if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&

	if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&

		     (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +

		      sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {

		u32 val;



		val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);

		val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;

		val &= ~tg3_lso_rd_dma_workaround_bit(tp);

		tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);

		tg3_flag_clear(tp, 5719_RDMA_BUG);

		tg3_flag_clear(tp, 5719_5720_RDMA_BUG);

	}



	TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);

drivers/net/ethernet/broadcom/tg3.h

+3 −2
Original line number Diff line number Diff line
@@ -1422,7 +1422,8 @@ 
#define TG3_LSO_RD_DMA_CRPTEN_CTRL	0x00004910

#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K	 0x00030000

#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K	 0x000c0000

#define TG3_LSO_RD_DMA_TX_LENGTH_WA	 0x02000000

#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719	 0x02000000

#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720	 0x00200000

/* 0x4914 --> 0x4be0 unused */



#define TG3_NUM_RDMA_CHANNELS		4
@@ -3059,7 +3060,7 @@ enum TG3_FLAGS { 
	TG3_FLAG_APE_HAS_NCSI,

	TG3_FLAG_TX_TSTAMP_EN,

	TG3_FLAG_4K_FIFO_LIMIT,

	TG3_FLAG_5719_RDMA_BUG,

	TG3_FLAG_5719_5720_RDMA_BUG,

	TG3_FLAG_RESET_TASK_PENDING,

	TG3_FLAG_PTP_CAPABLE,

	TG3_FLAG_5705_PLUS,