Merge "ARM: dts: msm: Add support for UART dtsi on sdxprairie" (9a7a8c99) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdxprairie-blsp.dtsi

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		@@ -297,4 +297,276 @@
		status = "disabled";
		};

		blsp1_uart1a_hs: uarta@82f000 { /* BLSP1 UART1: GPIO: 0,1,2,3 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x82f000 0x200>,
		<0x804000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart1a_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 24 0
		1 &intc 0 58 0
		2 &tlmm 1 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <0>;
		qcom,bam-rx-ep-pipe-index = <1>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>,
		<&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart1a_tx_sleep>,
		<&blsp1_uart1a_rxcts_sleep>, <&blsp1_uart1a_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart1a_tx_active>,
		<&blsp1_uart1a_rxcts_active>, <&blsp1_uart1a_rfr_active>;

		qcom,msm-bus,name = "buart1a";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<86 512 0 0>,
		<86 512 500 800>;
		status = "disabled";
		};

		blsp1_uart1b_hs: uartb@82f000 { /* BLSP1 UART1: GPIO: 20,21,22,23 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x82f000 0x200>,
		<0x804000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart1b_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 24 0
		1 &intc 0 58 0
		2 &tlmm 21 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <0>;
		qcom,bam-rx-ep-pipe-index = <1>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>,
		<&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart1b_tx_sleep>,
		<&blsp1_uart1b_rxcts_sleep>, <&blsp1_uart1b_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart1b_tx_active>,
		<&blsp1_uart1b_rxcts_active>, <&blsp1_uart1b_rfr_active>;

		qcom,msm-bus,name = "buart1b";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<86 512 0 0>,
		<86 512 500 800>;
		status = "disabled";
		};

		blsp1_uart2a_hs: uarta@830000 { /* BLSP1 UART2 : GPIO: 4,5,6,7 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x830000 0x200>,
		<0x804000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart2a_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 25 0
		1 &intc 0 58 0
		2 &tlmm 5 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <2>;
		qcom,bam-rx-ep-pipe-index = <3>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
		<&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart2a_tx_sleep>,
		<&blsp1_uart2a_rxcts_sleep>, <&blsp1_uart2a_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart2b_tx_active>,
		<&blsp1_uart2b_rxcts_active>, <&blsp1_uart2b_rfr_active>;

		qcom,msm-bus,name = "buart2a";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<86 512 0 0>,
		<86 512 500 800>;
		status = "disabled";
		};

		blsp1_uart2b_hs: uartb@830000 { /* BLSP1 UART2 : GPIO: 63,64,65,66 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x830000 0x200>,
		<0x804000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart2b_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 25 0
		1 &intc 0 58 0
		2 &tlmm 64 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <2>;
		qcom,bam-rx-ep-pipe-index = <3>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
		<&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart2b_tx_sleep>,
		<&blsp1_uart2b_rxcts_sleep>, <&blsp1_uart2b_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart2b_tx_active>,
		<&blsp1_uart2b_rxcts_active>, <&blsp1_uart2b_rfr_active>;

		qcom,msm-bus,name = "buart2b";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<86 512 0 0>,
		<86 512 500 800>;
		status = "disabled";
		};

		blsp1_uart3_hs: uart@831000 { /* BLSP1 UART3: GPIO: 8,9,10,11 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x831000 0x200>,
		<0x804000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart3_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 26 0
		1 &intc 0 58 0
		2 &tlmm 9 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <4>;
		qcom,bam-rx-ep-pipe-index = <5>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART3_APPS_CLK>,
		<&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart3_tx_sleep>,
		<&blsp1_uart3_rxcts_sleep>, <&blsp1_uart3_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart3_tx_active>,
		<&blsp1_uart3_rxcts_active>, <&blsp1_uart3_rfr_active>;

		qcom,msm-bus,name = "buart3";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<86 512 0 0>,
		<86 512 500 800>;
		status = "disabled";
		};

		blsp1_uart4a_hs: uarta@832000 { /* BLSP1 UART4 : GPIO: 20,21,22,23 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x832000 0x200>,
		<0x804000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart4a_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 27 0
		1 &intc 0 58 0
		2 &tlmm 21 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <6>;
		qcom,bam-rx-ep-pipe-index = <7>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART4_APPS_CLK>,
		<&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart4a_tx_active>,
		<&blsp1_uart4a_rxcts_sleep>, <&blsp1_uart4a_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart4a_tx_active>,
		<&blsp1_uart4a_rxcts_active>, <&blsp1_uart4a_rfr_active>;

		qcom,msm-bus,name = "buart4a";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<86 512 0 0>,
		<86 512 500 800>;
		status = "disabled";
		};

		blsp1_uart4b_hs: uartb@832000 { /* BLSP1 UART4 : GPIO: 16,17,18,19 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x832000 0x200>,
		<0x804000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart4b_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 27 0
		1 &intc 0 58 0
		2 &tlmm 17 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <6>;
		qcom,bam-rx-ep-pipe-index = <7>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART4_APPS_CLK>,
		<&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart4b_tx_sleep>,
		<&blsp1_uart4b_rxcts_sleep>, <&blsp1_uart4b_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart4b_tx_active>,
		<&blsp1_uart4b_rxcts_active>, <&blsp1_uart4b_rfr_active>;

		qcom,msm-bus,name = "buart4b";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<86 512 0 0>,
		<86 512 500 800>;
		status = "disabled";
		};
		};

arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi

+562 −0

Original line number	Diff line number	Diff line
		@@ -373,5 +373,567 @@
		};
		};


		/* HS UART CONFIGURATION */

		blsp1_uart1a: blsp1_uart1a {
		blsp1_uart1a_tx_active: blsp1_uart1a_tx_active {
		mux {
		pins = "gpio0";
		function = "blsp_uart1";
		};

		config {
		pins = "gpio0";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart1a_tx_sleep: blsp1_uart1a_tx_sleep {
		mux {
		pins = "gpio0";
		function = "gpio";
		};

		config {
		pins = "gpio0";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		blsp1_uart1a_rxcts_active: blsp1_uart1a_rxcts_active {
		mux {
		pins = "gpio1", "gpio2";
		function = "blsp_uart1";
		};

		config {
		pins = "gpio1", "gpio2";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart1a_rxcts_sleep: blsp1_uart1a_rxcts_sleep {
		mux {
		pins = "gpio1", "gpio2";
		function = "gpio";
		};

		config {
		pins = "gpio1", "gpio2";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		blsp1_uart1a_rfr_active: blsp1_uart1a_rfr_active {
		mux {
		pins = "gpio3";
		function = "blsp_uart1";
		};

		config {
		pins = "gpio3";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart1a_rfr_sleep: blsp1_uart1a_rfr_sleep {
		mux {
		pins = "gpio3";
		function = "gpio";
		};

		config {
		pins = "gpio3";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		blsp1_uart1b: blsp1_uart1b {
		blsp1_uart1b_tx_active: blsp1_uart1b_tx_active {
		mux {
		pins = "gpio20";
		function = "blsp_uart1";
		};

		config {
		pins = "gpio20";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart1b_tx_sleep: blsp1_uart1b_tx_sleep {
		mux {
		pins = "gpio20";
		function = "gpio";
		};

		config {
		pins = "gpio20";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		blsp1_uart1b_rxcts_active: blsp1_uart1b_rxcts_active {
		mux {
		pins = "gpio21", "gpio22";
		function = "blsp_uart1";
		};

		config {
		pins = "gpio21", "gpio22";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart1b_rxcts_sleep: blsp1_uart1b_rxcts_sleep {
		mux {
		pins = "gpio21", "gpio22";
		function = "gpio";
		};

		config {
		pins = "gpio21", "gpio22";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		blsp1_uart1b_rfr_active: blsp1_uart1b_rfr_active {
		mux {
		pins = "gpio23";
		function = "blsp_uart1";
		};

		config {
		pins = "gpio23";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart1b_rfr_sleep: blsp1_uart1b_rfr_sleep {
		mux {
		pins = "gpio23";
		function = "gpio";
		};

		config {
		pins = "gpio23";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		blsp1_uart2a: blsp1_uart2a {
		blsp1_uart2a_tx_active: blsp1_uart2a_tx_active {
		mux {
		pins = "gpio4";
		function = "blsp_uart2";
		};

		config {
		pins = "gpio4";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2a_tx_sleep: blsp1_uart2a_tx_sleep {
		mux {
		pins = "gpio4";
		function = "gpio";
		};

		config {
		pins = "gpio4";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		blsp1_uart2a_rxcts_active: blsp1_uart2a_rxcts_active {
		mux {
		pins = "gpio5", "gpio6";
		function = "blsp_uart2";
		};

		config {
		pins = "gpio5", "gpio6";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2a_rxcts_sleep: blsp1_uart2a_rxcts_sleep {
		mux {
		pins = "gpio5", "gpio6";
		function = "gpio";
		};

		config {
		pins = "gpio1", "gpio2";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		blsp1_uart2a_rfr_active: blsp1_uart2a_rfr_active {
		mux {
		pins = "gpio7";
		function = "blsp_uart2";
		};

		config {
		pins = "gpio7";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2a_rfr_sleep: blsp1_uart2a_rfr_sleep {
		mux {
		pins = "gpio7";
		function = "gpio";
		};

		config {
		pins = "gpio7";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		blsp1_uart2b: blsp1_uart2b {
		blsp1_uart2b_tx_active: blsp1_uart2b_tx_active {
		mux {
		pins = "gpio63";
		function = "blsp_uart2";
		};

		config {
		pins = "gpio63";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2b_tx_sleep: blsp1_uart2b_tx_sleep {
		mux {
		pins = "gpio63";
		function = "gpio";
		};

		config {
		pins = "gpio63";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		blsp1_uart2b_rxcts_active: blsp1_uart2b_rxcts_active {
		mux {
		pins = "gpio64", "gpio65";
		function = "blsp_uart2";
		};

		config {
		pins = "gpio64", "gpio65";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2b_rxcts_sleep: blsp1_uart2b_rxcts_sleep {
		mux {
		pins = "gpio64", "gpio65";
		function = "gpio";
		};

		config {
		pins = "gpio64", "gpio65";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		blsp1_uart2b_rfr_active: blsp1_uart2b_rfr_active {
		mux {
		pins = "gpio66";
		function = "blsp_uart2";
		};

		config {
		pins = "gpio66";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2b_rfr_sleep: blsp1_uart2b_rfr_sleep {
		mux {
		pins = "gpio66";
		function = "gpio";
		};

		config {
		pins = "gpio66";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		blsp1_uart3: blsp1_uart3 {
		blsp1_uart3_tx_active: blsp1_uart3_tx_active {
		mux {
		pins = "gpio8";
		function = "blsp_uart3";
		};

		config {
		pins = "gpio8";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep {
		mux {
		pins = "gpio8";
		function = "gpio";
		};

		config {
		pins = "gpio8";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active {
		mux {
		pins = "gpio9", "gpio10";
		function = "blsp_uart3";
		};

		config {
		pins = "gpio9", "gpio10";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep {
		mux {
		pins = "gpio9", "gpio10";
		function = "gpio";
		};

		config {
		pins = "gpio9", "gpio10";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		blsp1_uart3_rfr_active: blsp1_uart3_rfr_active {
		mux {
		pins = "gpio11";
		function = "blsp_uart3";
		};

		config {
		pins = "gpio11";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep {
		mux {
		pins = "gpio11";
		function = "gpio";
		};

		config {
		pins = "gpio11";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		blsp1_uart4a: blsp1_uart4a {
		blsp1_uart4a_tx_active: blsp1_uart4a_tx_active {
		mux {
		pins = "gpio20";
		function = "blsp_uart4";
		};

		config {
		pins = "gpio20";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart4a_tx_sleep: blsp1_uart4a_tx_sleep {
		mux {
		pins = "gpio20";
		function = "gpio";
		};

		config {
		pins = "gpio20";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		blsp1_uart4a_rxcts_active: blsp1_uart4a_rxcts_active {
		mux {
		pins = "gpio21", "gpio22";
		function = "blsp_uart4";
		};

		config {
		pins = "gpio21", "gpio22";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart4a_rxcts_sleep: blsp1_uart4a_rxcts_sleep {
		mux {
		pins = "gpio21", "gpio22";
		function = "gpio";
		};

		config {
		pins = "gpio21", "gpio22";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		blsp1_uart4a_rfr_active: blsp1_uart4a_rfr_active {
		mux {
		pins = "gpio23";
		function = "blsp_uart4";
		};

		config {
		pins = "gpio23";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart4a_rfr_sleep: blsp1_uart4a_rfr_sleep {
		mux {
		pins = "gpio23";
		function = "gpio";
		};

		config {
		pins = "gpio23";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		blsp1_uart4b: blsp1_uart4b {
		blsp1_uart4b_tx_active: blsp1_uart4b_tx_active {
		mux {
		pins = "gpio16";
		function = "blsp_uart4";
		};

		config {
		pins = "gpio16";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart4b_tx_sleep: blsp1_uart4b_tx_sleep {
		mux {
		pins = "gpio16";
		function = "gpio";
		};

		config {
		pins = "gpio16";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		blsp1_uart4b_rxcts_active: blsp1_uart4b_rxcts_active {
		mux {
		pins = "gpio17", "gpio18";
		function = "blsp_uart4";
		};

		config {
		pins = "gpio17", "gpio18";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart4b_rxcts_sleep: blsp1_uart4b_rxcts_sleep {
		mux {
		pins = "gpio17", "gpio18";
		function = "gpio";
		};

		config {
		pins = "gpio17", "gpio18";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		blsp1_uart4b_rfr_active: blsp1_uart4b_rfr_active {
		mux {
		pins = "gpio19";
		function = "blsp_uart4";
		};

		config {
		pins = "gpio19";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart4b_rfr_sleep: blsp1_uart4b_rfr_sleep {
		mux {
		pins = "gpio19";
		function = "gpio";
		};

		config {
		pins = "gpio19";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};
		};
		};