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Commit 9a71f302 authored by Amit Nischal's avatar Amit Nischal Committed by Gerrit - the friendly Code Review server
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clk: qcom: Add display clock controller driver for SDMMAGPIE 



Add support for the display clock controller found on SDMMAGPIE
based devices. This would allow display drivers to probe and
control their clocks.

Change-Id: I627d0c5e2ec133ba1a6ca63e60f5ba28eb23b93f
Signed-off-by: default avatarAmit Nischal <anischal@codeaurora.org>
parent ca3f4934

Documentation/devicetree/bindings/clock/qcom,dispcc.txt

+5 −2
Original line number Diff line number Diff line
@@ -2,8 +2,11 @@ Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding 
--------------------------------------------------------------------



Required properties :

- compatible : Shall contain "qcom,dispcc-sm8150" or "qcom,dispcc-sm8150-v2" or

				"qcom,dispcc-sm6150".

- compatible : Shall contain one of the following:

		"qcom,dispcc-sm8150",

		"qcom,dispcc-sm8150-v2",

		"qcom,dispcc-sm6150",

		"qcom,dispcc-sdmmagpie".

- reg : Shall contain base register location and length.

- reg-names: Address name. Must be "cc_base".

- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf

drivers/clk/qcom/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -396,6 +396,15 @@ config MSM_DISPCC_SM6150 
	  Say Y if you want to support display devices and functionality such as

	  splash screen.



config MSM_DISPCC_SDMMAGPIE

	tristate "SDMMAGPIE Display Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the display clock controller on Qualcomm Technologies, Inc

	  SDMMAGPIE devices.

	  Say Y if you want to support display devices and functionality such as

	  splash screen.



config MSM_GCC_SDMMAGPIE

	tristate "SDMMAGPIE Global Clock Controller"

	depends on COMMON_CLK_QCOM

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ obj-$(CONFIG_MSM_DEBUGCC_SM6150) += debugcc-sm6150.o 
obj-$(CONFIG_MSM_DEBUGCC_SM8150) += debugcc-sm8150.o

obj-$(CONFIG_MSM_DISPCC_SM6150) += dispcc-sm6150.o

obj-$(CONFIG_MSM_DISPCC_SM8150) += dispcc-sm8150.o

obj-$(CONFIG_MSM_DISPCC_SDMMAGPIE) += dispcc-sdmmagpie.o

obj-$(CONFIG_MDM_DEBUGCC_QCS405) += debugcc-qcs405.o

obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o

obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o

drivers/clk/qcom/dispcc-sdmmagpie.c

0 → 100644
+1162 −0

File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/qcom,dispcc-sdmmagpie.h

+38 −38
Original line number Diff line number Diff line
@@ -14,49 +14,49 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SDMMAGPIE_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SDMMAGPIE_H



#define DISP_CC_DEBUG_CLK					0

#define DISP_CC_PLL0						0

#define DISP_CC_MDSS_AHB_CLK					1

#define DISP_CC_MDSS_AHB_CLK_SRC				2

#define DISP_CC_MDSS_BYTE0_CLK					3

#define DISP_CC_MDSS_BYTE0_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_INTF_CLK				5

#define DISP_CC_MDSS_BYTE1_CLK					6

#define DISP_CC_MDSS_BYTE1_CLK_SRC				7

#define DISP_CC_MDSS_BYTE1_INTF_CLK				8

#define DISP_CC_MDSS_DP_AUX_CLK					9

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				10

#define DISP_CC_MDSS_DP_CRYPTO_CLK				11

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				12

#define DISP_CC_MDSS_DP_LINK_CLK				13

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				14

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				15

#define DISP_CC_MDSS_DP_PIXEL1_CLK				16

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				17

#define DISP_CC_MDSS_DP_PIXEL_CLK				18

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				19

#define DISP_CC_MDSS_ESC0_CLK					20

#define DISP_CC_MDSS_ESC0_CLK_SRC				21

#define DISP_CC_MDSS_ESC1_CLK					22

#define DISP_CC_MDSS_ESC1_CLK_SRC				23

#define DISP_CC_MDSS_MDP_CLK					24

#define DISP_CC_MDSS_MDP_CLK_SRC				25

#define DISP_CC_MDSS_MDP_LUT_CLK				26

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				27

#define DISP_CC_MDSS_PCLK0_CLK					28

#define DISP_CC_MDSS_PCLK0_CLK_SRC				29

#define DISP_CC_MDSS_PCLK1_CLK					30

#define DISP_CC_MDSS_PCLK1_CLK_SRC				31

#define DISP_CC_MDSS_ROT_CLK					32

#define DISP_CC_MDSS_ROT_CLK_SRC				33

#define DISP_CC_MDSS_RSCC_AHB_CLK				34

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				35

#define DISP_CC_MDSS_VSYNC_CLK					36

#define DISP_CC_MDSS_VSYNC_CLK_SRC				37

#define DISP_CC_PLL0						38

#define DISP_CC_PLL_TEST_CLK					39

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				5

#define DISP_CC_MDSS_BYTE0_INTF_CLK				6

#define DISP_CC_MDSS_BYTE1_CLK					7

#define DISP_CC_MDSS_BYTE1_CLK_SRC				8

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				9

#define DISP_CC_MDSS_BYTE1_INTF_CLK				10

#define DISP_CC_MDSS_DP_AUX_CLK					11

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				12

#define DISP_CC_MDSS_DP_CRYPTO_CLK				13

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				14

#define DISP_CC_MDSS_DP_LINK_CLK				15

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				16

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				17

#define DISP_CC_MDSS_DP_PIXEL1_CLK				18

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				19

#define DISP_CC_MDSS_DP_PIXEL_CLK				20

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				21

#define DISP_CC_MDSS_ESC0_CLK					22

#define DISP_CC_MDSS_ESC0_CLK_SRC				23

#define DISP_CC_MDSS_ESC1_CLK					24

#define DISP_CC_MDSS_ESC1_CLK_SRC				25

#define DISP_CC_MDSS_MDP_CLK					26

#define DISP_CC_MDSS_MDP_CLK_SRC				27

#define DISP_CC_MDSS_MDP_LUT_CLK				28

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				29

#define DISP_CC_MDSS_PCLK0_CLK					30

#define DISP_CC_MDSS_PCLK0_CLK_SRC				31

#define DISP_CC_MDSS_PCLK1_CLK					32

#define DISP_CC_MDSS_PCLK1_CLK_SRC				33

#define DISP_CC_MDSS_ROT_CLK					34

#define DISP_CC_MDSS_ROT_CLK_SRC				35

#define DISP_CC_MDSS_RSCC_AHB_CLK				36

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				37

#define DISP_CC_MDSS_VSYNC_CLK					38

#define DISP_CC_MDSS_VSYNC_CLK_SRC				39

#define DISP_CC_XO_CLK						40

#define DISP_CC_XO_CLK_SRC					41



#define MDSS_CORE_GDSC						0

#define DISP_CC_SLEEP_CLK					42

#define DISP_CC_SLEEP_CLK_SRC					43



#endif