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Commit 9a4af28a authored by Ritesh Kumar's avatar Ritesh Kumar Committed by Gerrit - the friendly Code Review server
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clk: qcom: mdss: Fix switched bit clk rate after suspend-resume 



After suspend-resume, bit clk rate should be cooresponding to
the switched clk rate. Currently,it is switching back to original
60fps clk rate. To fix this, add CLK_GET_RATE_NOCACHE flag for
vco clk in DSI 14nm pll so that after suspend-resume, clk is
calculated based on cached vco rate corresponding to the
switched bit clk rate.

Change-Id: Ib0445fcbb596e15a5ca4b6edbce7062173f2debb
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent db20cbe2

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -1145,7 +1145,7 @@ void pll_vco_unprepare_14nm(struct clk_hw *hw) 
		return;

		return;

	}

	}





	pll->vco_cached_rate = clk_hw_get_rate(hw);

	pll->vco_cached_rate = clk_get_rate(hw->clk);

	dsi_pll_disable(hw);

	dsi_pll_disable(hw);

}

}

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -80,6 +80,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = { 
			.name = "dsi0pll_vco_clk_14nm",

			.name = "dsi0pll_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_dsi_vco,

			.ops = &clk_ops_dsi_vco,

		},

		},

};

};
@@ -92,6 +93,7 @@ static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = { 
			.name = "dsi0pll_shadow_vco_clk_14nm",

			.name = "dsi0pll_shadow_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_shadow_dsi_vco,

			.ops = &clk_ops_shadow_dsi_vco,

		},

		},

};

};
@@ -106,6 +108,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = { 
			.name = "dsi1pll_vco_clk_14nm",

			.name = "dsi1pll_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_dsi_vco,

			.ops = &clk_ops_dsi_vco,

		},

		},

};

};
@@ -120,6 +123,7 @@ static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = { 
			.name = "dsi1pll_shadow_vco_clk_14nm",

			.name = "dsi1pll_shadow_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_shadow_dsi_vco,

			.ops = &clk_ops_shadow_dsi_vco,

		},

		},

};

};