Loading drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c +2 −2 Original line number Diff line number Diff line Loading @@ -1725,7 +1725,7 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) hw_cfg->len, sizeof(struct drm_msm_3d_gamut)); return; } op_mode = SDE_REG_READ(&ctx->hw, gamut_base); op_mode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->gamut_blk.base); payload = hw_cfg->payload; rc = sde_gamut_get_mode_info(SSPP, payload, &tbl_len, &tbl_off, &op_mode, &scale_off); Loading Loading @@ -1896,7 +1896,7 @@ void reg_dmav1_setup_vig_igcv5(struct sde_hw_pipe *ctx, void *cfg) if (!data) return; reg = SDE_REG_READ(&ctx->hw, igc_base); reg = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->igc_blk[0].base); lut_enable = (reg >> 8) & BIT(0); lut_sel = (reg >> 9) & BIT(0); /* select LUT table (0 or 1) when 1D LUT is in active mode */ Loading Loading
drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c +2 −2 Original line number Diff line number Diff line Loading @@ -1725,7 +1725,7 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) hw_cfg->len, sizeof(struct drm_msm_3d_gamut)); return; } op_mode = SDE_REG_READ(&ctx->hw, gamut_base); op_mode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->gamut_blk.base); payload = hw_cfg->payload; rc = sde_gamut_get_mode_info(SSPP, payload, &tbl_len, &tbl_off, &op_mode, &scale_off); Loading Loading @@ -1896,7 +1896,7 @@ void reg_dmav1_setup_vig_igcv5(struct sde_hw_pipe *ctx, void *cfg) if (!data) return; reg = SDE_REG_READ(&ctx->hw, igc_base); reg = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->igc_blk[0].base); lut_enable = (reg >> 8) & BIT(0); lut_sel = (reg >> 9) & BIT(0); /* select LUT table (0 or 1) when 1D LUT is in active mode */ Loading