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Commit 99d3cd27 authored by Inbar Karmy's avatar Inbar Karmy Committed by Saeed Mahameed
Browse files

net/mlx5: Fix FPGA capability location



Currently, FPGA capability is located in (mdev)->caps.hca_cur,
change the location to be (mdev)->caps.fpga,
since hca_cur is reserved for HCA device capabilities.

Fixes: e29341fb ("net/mlx5: FPGA, Add basic support for Innova")
Signed-off-by: default avatarInbar Karmy <inbark@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 38e8a5c0
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+2 −2
Original line number Original line Diff line number Diff line
@@ -71,11 +71,11 @@ int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
	return 0;
	return 0;
}
}


int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps)
int mlx5_fpga_caps(struct mlx5_core_dev *dev)
{
{
	u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
	u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};


	return mlx5_core_access_reg(dev, in, sizeof(in), caps,
	return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
				    MLX5_ST_SZ_BYTES(fpga_cap),
				    MLX5_ST_SZ_BYTES(fpga_cap),
				    MLX5_REG_FPGA_CAP, 0, 0);
				    MLX5_REG_FPGA_CAP, 0, 0);
}
}
+1 −1
Original line number Original line Diff line number Diff line
@@ -65,7 +65,7 @@ struct mlx5_fpga_qp_counters {
	u64 rx_total_drop;
	u64 rx_total_drop;
};
};


int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps);
int mlx5_fpga_caps(struct mlx5_core_dev *dev);
int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
+1 −2
Original line number Original line Diff line number Diff line
@@ -139,8 +139,7 @@ int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
	if (err)
	if (err)
		goto out;
		goto out;


	err = mlx5_fpga_caps(fdev->mdev,
	err = mlx5_fpga_caps(fdev->mdev);
			     fdev->mdev->caps.hca_cur[MLX5_CAP_FPGA]);
	if (err)
	if (err)
		goto out;
		goto out;


+2 −3
Original line number Original line Diff line number Diff line
@@ -980,7 +980,6 @@ enum mlx5_cap_type {
	MLX5_CAP_RESERVED,
	MLX5_CAP_RESERVED,
	MLX5_CAP_VECTOR_CALC,
	MLX5_CAP_VECTOR_CALC,
	MLX5_CAP_QOS,
	MLX5_CAP_QOS,
	MLX5_CAP_FPGA,
	/* NUM OF CAP Types */
	/* NUM OF CAP Types */
	MLX5_CAP_NUM
	MLX5_CAP_NUM
};
};
@@ -1110,10 +1109,10 @@ enum mlx5_mcam_feature_groups {
	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)


#define MLX5_CAP_FPGA(mdev, cap) \
#define MLX5_CAP_FPGA(mdev, cap) \
	MLX5_GET(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap)
	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)


#define MLX5_CAP64_FPGA(mdev, cap) \
#define MLX5_CAP64_FPGA(mdev, cap) \
	MLX5_GET64(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap)
	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)


enum {
enum {
	MLX5_CMD_STAT_OK			= 0x0,
	MLX5_CMD_STAT_OK			= 0x0,
+1 −0
Original line number Original line Diff line number Diff line
@@ -774,6 +774,7 @@ struct mlx5_core_dev {
		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
	} caps;
	} caps;
	phys_addr_t		iseg_base;
	phys_addr_t		iseg_base;
	struct mlx5_init_seg __iomem *iseg;
	struct mlx5_init_seg __iomem *iseg;