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Commit 99861ab8 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Initial implementation of A6XX RGMU driver"

parents f63747b8 38012595

Documentation/devicetree/bindings/gpu/adreno-gmu.txt

+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU) 
Required properties:

- compatible :

	- "qcom,gpu-gmu"

	- "qcom,gpu-rgmu"

- reg:		Specifies the PDC register base address and size.

- reg-names:		Resource names used for the physical address

		and length of PDC registers.

drivers/gpu/msm/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ msm_kgsl_core-y = \ 
	kgsl_pool.o \

	kgsl_gmu_core.o \

	kgsl_gmu.o \

	kgsl_rgmu.o \

	kgsl_hfi.o



msm_kgsl_core-$(CONFIG_QCOM_KGSL_IOMMU) += kgsl_iommu.o
@@ -41,6 +42,7 @@ msm_adreno-y += \ 
	adreno_a5xx_preempt.o \

	adreno_a6xx_preempt.o \

	adreno_a6xx_gmu.o \

	adreno_a6xx_rgmu.o \

	adreno_sysfs.o \

	adreno.o \

	adreno_cp_parser.o \

drivers/gpu/msm/a6xx_reg.h

+18 −0
Original line number Diff line number Diff line
@@ -412,11 +412,13 @@ 
#define A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0001f

#define A6XX_RBBM_INT_CLEAR_CMD          0x00037

#define A6XX_RBBM_INT_0_MASK             0x00038

#define A6XX_RBBM_INT_2_MASK             0x0003A

#define A6XX_RBBM_SP_HYST_CNT            0x00042

#define A6XX_RBBM_SW_RESET_CMD           0x00043

#define A6XX_RBBM_RAC_THRESHOLD_CNT      0x00044

#define A6XX_RBBM_BLOCK_SW_RESET_CMD     0x00045

#define A6XX_RBBM_BLOCK_SW_RESET_CMD2    0x00046

#define A6XX_RBBM_BLOCK_GX_RETENTION_CNTL 0x00050

#define A6XX_RBBM_CLOCK_CNTL             0x000ae

#define A6XX_RBBM_CLOCK_CNTL_SP0         0x000b0

#define A6XX_RBBM_CLOCK_CNTL_SP1         0x000b1
@@ -1026,6 +1028,11 @@ 
#define A6XX_GMU_RBBM_INT_UNMASKED_STATUS	0x23B15

#define A6XX_GMU_AO_SPARE_CNTL			0x23B16



/* RGMU GLM registers */

#define A6XX_GMU_AO_RGMU_GLM_SLEEP_CTRL		0x23B80

#define A6XX_GMU_AO_RGMU_GLM_SLEEP_STATUS	0x23B81

#define A6XX_GMU_AO_RGMU_GLM_HW_CRC_DISABLE	0x23B82



/* GMU RSC control registers */

#define A6XX_GPU_RSCC_RSC_STATUS0_DRV0		0x23404

#define A6XX_GMU_RSCC_CONTROL_REQ		0x23B07
@@ -1093,5 +1100,16 @@ 
 */

#define PDC_GPU_SEQ_MEM_0			0x0



/* RGMU(PCC) registers in A6X_GMU_CX_0_NON_CONTEXT_DEC domain */

#define A6XX_RGMU_CX_INTR_GEN_EN		0x1F80F

#define A6XX_RGMU_CX_RGMU_TIMER0		0x1F834

#define A6XX_RGMU_CX_RGMU_TIMER1		0x1F835

#define A6XX_RGMU_CX_PCC_CTRL			0x1F838

#define A6XX_RGMU_CX_PCC_INIT_RESULT		0x1F839

#define A6XX_RGMU_CX_PCC_BKPT_CFG		0x1F83A

#define A6XX_RGMU_CX_PCC_BKPT_ADDR		0x1F83B

#define A6XX_RGMU_CX_PCC_STATUS			0x1F83C

#define A6XX_RGMU_CX_PCC_DEBUG			0x1F83D



#endif /* _A6XX_REG_H */

drivers/gpu/msm/adreno-gpulist.h

+2 −1
Original line number Diff line number Diff line
@@ -449,13 +449,14 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.minor = 8,

		.patchid = ANY_ID,

		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION,

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a608_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = (SZ_128K + SZ_4K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a608_rgmu.bin",

	},

	{

		.gpurev = ADRENO_REV_A616,

drivers/gpu/msm/adreno.c

+3 −0
Original line number Diff line number Diff line
@@ -2168,6 +2168,9 @@ static int adreno_stop(struct kgsl_device *device) 
	/* Save physical performance counter values before GPU power down*/

	adreno_perfcounter_save(adreno_dev);



	if (GMU_DEV_OP_VALID(gmu_dev_ops, prepare_stop))

		gmu_dev_ops->prepare_stop(adreno_dev);



	if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear))

		gmu_dev_ops->oob_clear(adreno_dev, oob_gpu);