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Commit 99161524 authored by Guennadi Liakhovetski's avatar Guennadi Liakhovetski Committed by Simon Horman
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ARM: sh7372: fix cache clean / invalidate order 



According to the Cortex A8 TRM the L2 cache should be first cleaned and
then disabled. Fix the swapped order on sh7372.

Signed-off-by: default avatarGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Reviewed-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 529a7b32

arch/arm/mach-shmobile/sleep-sh7372.S

+7 −5
Original line number Diff line number Diff line
@@ -59,16 +59,18 @@ sh7372_do_idle_sysc: 
	mcr	p15, 0, r0, c1, c0, 0

	isb



	/*

	 * Clean and invalidate data cache again.

	 */

	ldr	r1, kernel_flush

	blx	r1



	/* disable L2 cache in the aux control register */

	mrc     p15, 0, r10, c1, c0, 1

	bic     r10, r10, #2

	mcr     p15, 0, r10, c1, c0, 1

	isb



	/*

	 * Invalidate data cache again.

	 */

	ldr	r1, kernel_flush

	blx	r1

	/*

	 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will

	 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.