Merge branch 'perf/urgent' into perf/core, to pick up fixes and refresh the branch

$(MEDIA_OBJ_DIR)/v4l2.xml: $(OBJIMGFILES)

	@$($(quiet)gen_xml)

	@(ln -sf $(MEDIA_SRC_DIR)/v4l/*xml $(MEDIA_OBJ_DIR)/)

	@(ln -sf $(MEDIA_SRC_DIR)/dvb/*xml $(MEDIA_OBJ_DIR)/)

	@(ln -sf `cd $(MEDIA_SRC_DIR) && /bin/pwd`/v4l/*xml $(MEDIA_OBJ_DIR)/)

	@(ln -sf `cd $(MEDIA_SRC_DIR) && /bin/pwd`/dvb/*xml $(MEDIA_OBJ_DIR)/)

$(MEDIA_OBJ_DIR)/videodev2.h.xml: $(srctree)/include/uapi/linux/videodev2.h $(MEDIA_OBJ_DIR)/v4l2.xml

	@$($(quiet)gen_xml)

	"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13

	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s

	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20

	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31

	"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31

	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31

	"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock

	"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31

	"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10

	"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13

	"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s

	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31

	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20

	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock

	"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing

	"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31

	"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20

	"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13

	"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31

Required properties for all clocks:

- reg : shall be the control register address for the clock.

[2] Documentation/devicetree/bindings/clock/ti/dpll.txt

Required properties:

- compatible : shall be "ti,dra7-apll-clock"

- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"

- #clock-cells : from common clock binding; shall be set to 0.

- clocks : link phandles of parent clocks (clk-ref and clk-bypass)

- reg : address and length of the register set for controlling the APLL.

  It contains the information of registers in the following order:

	"control" - contains the control register base address

	"idlest" - contains the idlest register base address

	"control" - contains the control register offset

	"idlest" - contains the idlest register offset

	"autoidle" - contains the autoidle register offset (OMAP2 only)

- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)

- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)

- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)

Examples:

	apll_pcie_ck: apll_pcie_ck@4a008200 {

	apll_pcie_ck: apll_pcie_ck {

		#clock-cells = <0>;

		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;

		reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;

		reg = <0x021c>, <0x0220>;

		compatible = "ti,dra7-apll-clock";

	};

	apll96_ck: apll96_ck {

		#clock-cells = <0>;

		compatible = "ti,omap2-apll-clock";

		clocks = <&sys_ck>;

		ti,bit-shift = <2>;

		ti,idlest-shift = <8>;

		ti,clock-frequency = <96000000>;

		reg = <0x0500>, <0x0530>, <0x0520>;

	};

		"ti,omap4-dpll-core-clock",

		"ti,omap4-dpll-m4xen-clock",

		"ti,omap4-dpll-j-type-clock",

		"ti,omap5-mpu-dpll-clock",

		"ti,am3-dpll-no-gate-clock",

		"ti,am3-dpll-j-type-clock",

		"ti,am3-dpll-no-gate-j-type-clock",

		"ti,am3-dpll-clock",

		"ti,am3-dpll-core-clock",

		"ti,am3-dpll-x2-clock",

		"ti,omap2-dpll-core-clock",

- #clock-cells : from common clock binding; shall be set to 0.

- clocks : link phandles of parent clocks, first entry lists reference clock

	"mult-div1" - contains the multiplier / divider register base address

	"autoidle" - contains the autoidle register base address (optional)

  ti,am3-* dpll types do not have autoidle register

  ti,omap2-* dpll type does not support idlest / autoidle registers

Optional properties:

- DPLL mode setting - defining any one or more of the following overrides

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x90>, <0x5c>, <0x68>;

	};

	dpll_ck: dpll_ck {

		#clock-cells = <0>;

		compatible = "ti,omap2-dpll-core-clock";

		clocks = <&sys_ck>, <&sys_ck>;

		reg = <0x0500>, <0x0540>;

	};

Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.

The ATL IP is used to generate clock to be used to synchronize baseband and

audio codec. A single ATL IP provides four ATL clock instances sharing the same

functional clock but can be configured to provide different clocks.

ATL can maintain a clock averages to some desired frequency based on the bws/aws

signals - can compensate the drift between the two ws signal.

In order to provide the support for ATL and it's output clocks (which can be used

internally within the SoC or external components) two sets of bindings is needed:

Clock tree binding:

This binding uses the common clock binding[1].

To be able to integrate the ATL clocks with DT clock tree.

Provides ccf level representation of the ATL clocks to be used by drivers.

Since the clock instances are part of a single IP this binding is used as a node

for the DT clock tree, the IP driver is needed to handle the actual configuration

of the IP.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- compatible : shall be "ti,dra7-atl-clock"

- #clock-cells : from common clock binding; shall be set to 0.

- clocks : link phandles to functional clock of ATL

Binding for the IP driver:

This binding is used to configure the IP driver which is going to handle the

configuration of the IP for the ATL clock instances.

Required properties:

- compatible : shall be "ti,dra7-atl"

- reg : base address for the ATL IP

- ti,provided-clocks : List of phandles to the clocks associated with the ATL

- clocks : link phandles to functional clock of ATL

- clock-names : Shall be set to "fck"

- ti,hwmods : Shall be set to "atl"

Optional properties:

Configuration of ATL instances:

- atl{0/1/2/3} {

	- bws : Baseband word select signal selection

	- aws : Audio word select signal selection

};

For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include

file.

Examples:

/* clock bindings for atl provided clocks */

atl_clkin0_ck: atl_clkin0_ck {

	#clock-cells = <0>;

	compatible = "ti,dra7-atl-clock";

	clocks = <&atl_gfclk_mux>;

};

atl_clkin1_ck: atl_clkin1_ck {

	#clock-cells = <0>;

	compatible = "ti,dra7-atl-clock";

	clocks = <&atl_gfclk_mux>;

};

atl_clkin2_ck: atl_clkin2_ck {

	#clock-cells = <0>;

	compatible = "ti,dra7-atl-clock";

	clocks = <&atl_gfclk_mux>;

};

atl_clkin3_ck: atl_clkin3_ck {

	#clock-cells = <0>;

	compatible = "ti,dra7-atl-clock";

	clocks = <&atl_gfclk_mux>;

};

/* binding for the IP */

atl: atl@4843c000 {

	compatible = "ti,dra7-atl";

	reg = <0x4843c000 0x3ff>;

	ti,hwmods = "atl";

	ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,

				<&atl_clkin2_ck>, <&atl_clkin3_ck>;

	clocks = <&atl_gfclk_mux>;

	clock-names = "fck";

	status = "disabled";

};

#include <dt-bindings/clk/ti-dra7-atl.h>

&atl {

	status = "okay";

	atl2 {

		bws = <DRA7_ATL_WS_MCASP2_FSX>;

		aws = <DRA7_ATL_WS_MCASP3_FSX>;

	};

};