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Commit 98c33c5a authored by Will Deacon's avatar Will Deacon Committed by Joerg Roedel
Browse files

documentation/iommu: Add description of ARM System MMU binding 



This patch adds a description of the device tree binding for the ARM
System MMU architecture.

Cc: Rob Herring <robherring2@gmail.com>
Cc: Andreas Herrmann <andreas.herrmann@calxeda.com>
Cc: Joerg Roedel <joro@8bytes.org>
Acked-by: default avatarGrant Likely <grant.likely@linaro.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Acked-by: default avatarAndreas Herrmann <andreas.herrmann@calxeda.com>
Signed-off-by: default avatarJoerg Roedel <joro@8bytes.org>
parent 9e895ace

Documentation/devicetree/bindings/iommu/arm,smmu.txt

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+70 −0
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* ARM System MMU Architecture Implementation



ARM SoCs may contain an implementation of the ARM System Memory

Management Unit Architecture, which can be used to provide 1 or 2 stages

of address translation to bus masters external to the CPU.



The SMMU may also raise interrupts in response to various fault

conditions.



** System MMU required properties:



- compatible    : Should be one of:



                        "arm,smmu-v1"

                        "arm,smmu-v2"

                        "arm,mmu-400"

                        "arm,mmu-500"



                  depending on the particular implementation and/or the

                  version of the architecture implemented.



- reg           : Base address and size of the SMMU.



- #global-interrupts : The number of global interrupts exposed by the

                       device.



- interrupts    : Interrupt list, with the first #global-irqs entries

                  corresponding to the global interrupts and any

                  following entries corresponding to context interrupts,

                  specified in order of their indexing by the SMMU.



                  For SMMUv2 implementations, there must be exactly one

                  interrupt per context bank. In the case of a single,

                  combined interrupt, it must be listed multiple times.



- mmu-masters   : A list of phandles to device nodes representing bus

                  masters for which the SMMU can provide a translation

                  and their corresponding StreamIDs (see example below).

                  Each device node linked from this list must have a

                  "#stream-id-cells" property, indicating the number of

                  StreamIDs associated with it.



** System MMU optional properties:



- smmu-parent   : When multiple SMMUs are chained together, this

                  property can be used to provide a phandle to the

                  parent SMMU (that is the next SMMU on the path going

                  from the mmu-masters towards memory) node for this

                  SMMU.



Example:



        smmu {

                compatible = "arm,smmu-v1";

                reg = <0xba5e0000 0x10000>;

                #global-interrupts = <2>;

                interrupts = <0 32 4>,

                             <0 33 4>,

                             <0 34 4>, /* This is the first context interrupt */

                             <0 35 4>,

                             <0 36 4>,

                             <0 37 4>;



                /*

                 * Two DMA controllers, the first with two StreamIDs (0xd01d

                 * and 0xd01e) and the second with only one (0xd11c).

                 */

                mmu-masters = <&dma0 0xd01d 0xd01e>,

                              <&dma1 0xd11c>;

        };