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Commit 98b0429b authored by Ralf Baechle's avatar Ralf Baechle
Browse files

Merge branch '4.1-fp' into mips-for-linux-next

parents 3cf29543 1f3a2c6e

arch/mips/include/asm/asmmacro-32.h

+32 −32
Original line number Diff line number Diff line
@@ -16,22 +16,22 @@ 
	.set push

	SET_HARDFLOAT

	cfc1	\tmp,  fcr31

	s.d	$f0,  THREAD_FPR0_LS64(\thread)

	s.d	$f2,  THREAD_FPR2_LS64(\thread)

	s.d	$f4,  THREAD_FPR4_LS64(\thread)

	s.d	$f6,  THREAD_FPR6_LS64(\thread)

	s.d	$f8,  THREAD_FPR8_LS64(\thread)

	s.d	$f10, THREAD_FPR10_LS64(\thread)

	s.d	$f12, THREAD_FPR12_LS64(\thread)

	s.d	$f14, THREAD_FPR14_LS64(\thread)

	s.d	$f16, THREAD_FPR16_LS64(\thread)

	s.d	$f18, THREAD_FPR18_LS64(\thread)

	s.d	$f20, THREAD_FPR20_LS64(\thread)

	s.d	$f22, THREAD_FPR22_LS64(\thread)

	s.d	$f24, THREAD_FPR24_LS64(\thread)

	s.d	$f26, THREAD_FPR26_LS64(\thread)

	s.d	$f28, THREAD_FPR28_LS64(\thread)

	s.d	$f30, THREAD_FPR30_LS64(\thread)

	s.d	$f0,  THREAD_FPR0(\thread)

	s.d	$f2,  THREAD_FPR2(\thread)

	s.d	$f4,  THREAD_FPR4(\thread)

	s.d	$f6,  THREAD_FPR6(\thread)

	s.d	$f8,  THREAD_FPR8(\thread)

	s.d	$f10, THREAD_FPR10(\thread)

	s.d	$f12, THREAD_FPR12(\thread)

	s.d	$f14, THREAD_FPR14(\thread)

	s.d	$f16, THREAD_FPR16(\thread)

	s.d	$f18, THREAD_FPR18(\thread)

	s.d	$f20, THREAD_FPR20(\thread)

	s.d	$f22, THREAD_FPR22(\thread)

	s.d	$f24, THREAD_FPR24(\thread)

	s.d	$f26, THREAD_FPR26(\thread)

	s.d	$f28, THREAD_FPR28(\thread)

	s.d	$f30, THREAD_FPR30(\thread)

	sw	\tmp, THREAD_FCR31(\thread)

	.set pop

	.endm
@@ -40,22 +40,22 @@ 
	.set push

	SET_HARDFLOAT

	lw	\tmp, THREAD_FCR31(\thread)

	l.d	$f0,  THREAD_FPR0_LS64(\thread)

	l.d	$f2,  THREAD_FPR2_LS64(\thread)

	l.d	$f4,  THREAD_FPR4_LS64(\thread)

	l.d	$f6,  THREAD_FPR6_LS64(\thread)

	l.d	$f8,  THREAD_FPR8_LS64(\thread)

	l.d	$f10, THREAD_FPR10_LS64(\thread)

	l.d	$f12, THREAD_FPR12_LS64(\thread)

	l.d	$f14, THREAD_FPR14_LS64(\thread)

	l.d	$f16, THREAD_FPR16_LS64(\thread)

	l.d	$f18, THREAD_FPR18_LS64(\thread)

	l.d	$f20, THREAD_FPR20_LS64(\thread)

	l.d	$f22, THREAD_FPR22_LS64(\thread)

	l.d	$f24, THREAD_FPR24_LS64(\thread)

	l.d	$f26, THREAD_FPR26_LS64(\thread)

	l.d	$f28, THREAD_FPR28_LS64(\thread)

	l.d	$f30, THREAD_FPR30_LS64(\thread)

	l.d	$f0,  THREAD_FPR0(\thread)

	l.d	$f2,  THREAD_FPR2(\thread)

	l.d	$f4,  THREAD_FPR4(\thread)

	l.d	$f6,  THREAD_FPR6(\thread)

	l.d	$f8,  THREAD_FPR8(\thread)

	l.d	$f10, THREAD_FPR10(\thread)

	l.d	$f12, THREAD_FPR12(\thread)

	l.d	$f14, THREAD_FPR14(\thread)

	l.d	$f16, THREAD_FPR16(\thread)

	l.d	$f18, THREAD_FPR18(\thread)

	l.d	$f20, THREAD_FPR20(\thread)

	l.d	$f22, THREAD_FPR22(\thread)

	l.d	$f24, THREAD_FPR24(\thread)

	l.d	$f26, THREAD_FPR26(\thread)

	l.d	$f28, THREAD_FPR28(\thread)

	l.d	$f30, THREAD_FPR30(\thread)

	ctc1	\tmp, fcr31

	.set pop

	.endm

arch/mips/include/asm/asmmacro.h

+127 −91
Original line number Diff line number Diff line
@@ -60,22 +60,22 @@ 
	.set	push

	SET_HARDFLOAT

	cfc1	\tmp, fcr31

	sdc1	$f0,  THREAD_FPR0_LS64(\thread)

	sdc1	$f2,  THREAD_FPR2_LS64(\thread)

	sdc1	$f4,  THREAD_FPR4_LS64(\thread)

	sdc1	$f6,  THREAD_FPR6_LS64(\thread)

	sdc1	$f8,  THREAD_FPR8_LS64(\thread)

	sdc1	$f10, THREAD_FPR10_LS64(\thread)

	sdc1	$f12, THREAD_FPR12_LS64(\thread)

	sdc1	$f14, THREAD_FPR14_LS64(\thread)

	sdc1	$f16, THREAD_FPR16_LS64(\thread)

	sdc1	$f18, THREAD_FPR18_LS64(\thread)

	sdc1	$f20, THREAD_FPR20_LS64(\thread)

	sdc1	$f22, THREAD_FPR22_LS64(\thread)

	sdc1	$f24, THREAD_FPR24_LS64(\thread)

	sdc1	$f26, THREAD_FPR26_LS64(\thread)

	sdc1	$f28, THREAD_FPR28_LS64(\thread)

	sdc1	$f30, THREAD_FPR30_LS64(\thread)

	sdc1	$f0,  THREAD_FPR0(\thread)

	sdc1	$f2,  THREAD_FPR2(\thread)

	sdc1	$f4,  THREAD_FPR4(\thread)

	sdc1	$f6,  THREAD_FPR6(\thread)

	sdc1	$f8,  THREAD_FPR8(\thread)

	sdc1	$f10, THREAD_FPR10(\thread)

	sdc1	$f12, THREAD_FPR12(\thread)

	sdc1	$f14, THREAD_FPR14(\thread)

	sdc1	$f16, THREAD_FPR16(\thread)

	sdc1	$f18, THREAD_FPR18(\thread)

	sdc1	$f20, THREAD_FPR20(\thread)

	sdc1	$f22, THREAD_FPR22(\thread)

	sdc1	$f24, THREAD_FPR24(\thread)

	sdc1	$f26, THREAD_FPR26(\thread)

	sdc1	$f28, THREAD_FPR28(\thread)

	sdc1	$f30, THREAD_FPR30(\thread)

	sw	\tmp, THREAD_FCR31(\thread)

	.set	pop

	.endm
@@ -84,22 +84,22 @@ 
	.set	push

	.set	mips64r2

	SET_HARDFLOAT

	sdc1	$f1,  THREAD_FPR1_LS64(\thread)

	sdc1	$f3,  THREAD_FPR3_LS64(\thread)

	sdc1	$f5,  THREAD_FPR5_LS64(\thread)

	sdc1	$f7,  THREAD_FPR7_LS64(\thread)

	sdc1	$f9,  THREAD_FPR9_LS64(\thread)

	sdc1	$f11, THREAD_FPR11_LS64(\thread)

	sdc1	$f13, THREAD_FPR13_LS64(\thread)

	sdc1	$f15, THREAD_FPR15_LS64(\thread)

	sdc1	$f17, THREAD_FPR17_LS64(\thread)

	sdc1	$f19, THREAD_FPR19_LS64(\thread)

	sdc1	$f21, THREAD_FPR21_LS64(\thread)

	sdc1	$f23, THREAD_FPR23_LS64(\thread)

	sdc1	$f25, THREAD_FPR25_LS64(\thread)

	sdc1	$f27, THREAD_FPR27_LS64(\thread)

	sdc1	$f29, THREAD_FPR29_LS64(\thread)

	sdc1	$f31, THREAD_FPR31_LS64(\thread)

	sdc1	$f1,  THREAD_FPR1(\thread)

	sdc1	$f3,  THREAD_FPR3(\thread)

	sdc1	$f5,  THREAD_FPR5(\thread)

	sdc1	$f7,  THREAD_FPR7(\thread)

	sdc1	$f9,  THREAD_FPR9(\thread)

	sdc1	$f11, THREAD_FPR11(\thread)

	sdc1	$f13, THREAD_FPR13(\thread)

	sdc1	$f15, THREAD_FPR15(\thread)

	sdc1	$f17, THREAD_FPR17(\thread)

	sdc1	$f19, THREAD_FPR19(\thread)

	sdc1	$f21, THREAD_FPR21(\thread)

	sdc1	$f23, THREAD_FPR23(\thread)

	sdc1	$f25, THREAD_FPR25(\thread)

	sdc1	$f27, THREAD_FPR27(\thread)

	sdc1	$f29, THREAD_FPR29(\thread)

	sdc1	$f31, THREAD_FPR31(\thread)

	.set	pop

	.endm
@@ -118,22 +118,22 @@ 
	.set	push

	SET_HARDFLOAT

	lw	\tmp, THREAD_FCR31(\thread)

	ldc1	$f0,  THREAD_FPR0_LS64(\thread)

	ldc1	$f2,  THREAD_FPR2_LS64(\thread)

	ldc1	$f4,  THREAD_FPR4_LS64(\thread)

	ldc1	$f6,  THREAD_FPR6_LS64(\thread)

	ldc1	$f8,  THREAD_FPR8_LS64(\thread)

	ldc1	$f10, THREAD_FPR10_LS64(\thread)

	ldc1	$f12, THREAD_FPR12_LS64(\thread)

	ldc1	$f14, THREAD_FPR14_LS64(\thread)

	ldc1	$f16, THREAD_FPR16_LS64(\thread)

	ldc1	$f18, THREAD_FPR18_LS64(\thread)

	ldc1	$f20, THREAD_FPR20_LS64(\thread)

	ldc1	$f22, THREAD_FPR22_LS64(\thread)

	ldc1	$f24, THREAD_FPR24_LS64(\thread)

	ldc1	$f26, THREAD_FPR26_LS64(\thread)

	ldc1	$f28, THREAD_FPR28_LS64(\thread)

	ldc1	$f30, THREAD_FPR30_LS64(\thread)

	ldc1	$f0,  THREAD_FPR0(\thread)

	ldc1	$f2,  THREAD_FPR2(\thread)

	ldc1	$f4,  THREAD_FPR4(\thread)

	ldc1	$f6,  THREAD_FPR6(\thread)

	ldc1	$f8,  THREAD_FPR8(\thread)

	ldc1	$f10, THREAD_FPR10(\thread)

	ldc1	$f12, THREAD_FPR12(\thread)

	ldc1	$f14, THREAD_FPR14(\thread)

	ldc1	$f16, THREAD_FPR16(\thread)

	ldc1	$f18, THREAD_FPR18(\thread)

	ldc1	$f20, THREAD_FPR20(\thread)

	ldc1	$f22, THREAD_FPR22(\thread)

	ldc1	$f24, THREAD_FPR24(\thread)

	ldc1	$f26, THREAD_FPR26(\thread)

	ldc1	$f28, THREAD_FPR28(\thread)

	ldc1	$f30, THREAD_FPR30(\thread)

	ctc1	\tmp, fcr31

	.endm
@@ -141,22 +141,22 @@ 
	.set	push

	.set	mips64r2

	SET_HARDFLOAT

	ldc1	$f1,  THREAD_FPR1_LS64(\thread)

	ldc1	$f3,  THREAD_FPR3_LS64(\thread)

	ldc1	$f5,  THREAD_FPR5_LS64(\thread)

	ldc1	$f7,  THREAD_FPR7_LS64(\thread)

	ldc1	$f9,  THREAD_FPR9_LS64(\thread)

	ldc1	$f11, THREAD_FPR11_LS64(\thread)

	ldc1	$f13, THREAD_FPR13_LS64(\thread)

	ldc1	$f15, THREAD_FPR15_LS64(\thread)

	ldc1	$f17, THREAD_FPR17_LS64(\thread)

	ldc1	$f19, THREAD_FPR19_LS64(\thread)

	ldc1	$f21, THREAD_FPR21_LS64(\thread)

	ldc1	$f23, THREAD_FPR23_LS64(\thread)

	ldc1	$f25, THREAD_FPR25_LS64(\thread)

	ldc1	$f27, THREAD_FPR27_LS64(\thread)

	ldc1	$f29, THREAD_FPR29_LS64(\thread)

	ldc1	$f31, THREAD_FPR31_LS64(\thread)

	ldc1	$f1,  THREAD_FPR1(\thread)

	ldc1	$f3,  THREAD_FPR3(\thread)

	ldc1	$f5,  THREAD_FPR5(\thread)

	ldc1	$f7,  THREAD_FPR7(\thread)

	ldc1	$f9,  THREAD_FPR9(\thread)

	ldc1	$f11, THREAD_FPR11(\thread)

	ldc1	$f13, THREAD_FPR13(\thread)

	ldc1	$f15, THREAD_FPR15(\thread)

	ldc1	$f17, THREAD_FPR17(\thread)

	ldc1	$f19, THREAD_FPR19(\thread)

	ldc1	$f21, THREAD_FPR21(\thread)

	ldc1	$f23, THREAD_FPR23(\thread)

	ldc1	$f25, THREAD_FPR25(\thread)

	ldc1	$f27, THREAD_FPR27(\thread)

	ldc1	$f29, THREAD_FPR29(\thread)

	ldc1	$f31, THREAD_FPR31(\thread)

	.set	pop

	.endm
@@ -211,6 +211,22 @@ 
	.endm



#ifdef TOOLCHAIN_SUPPORTS_MSA

	.macro	_cfcmsa	rd, cs

	.set	push

	.set	mips32r2

	.set	msa

	cfcmsa	\rd, $\cs

	.set	pop

	.endm



	.macro	_ctcmsa	cd, rs

	.set	push

	.set	mips32r2

	.set	msa

	ctcmsa	$\cd, \rs

	.set	pop

	.endm



	.macro	ld_d	wd, off, base

	.set	push

	.set	mips32r2
@@ -227,35 +243,35 @@ 
	.set	pop

	.endm



	.macro	copy_u_w	rd, ws, n

	.macro	copy_u_w	ws, n

	.set	push

	.set	mips32r2

	.set	msa

	copy_u.w \rd, $w\ws[\n]

	copy_u.w $1, $w\ws[\n]

	.set	pop

	.endm



	.macro	copy_u_d	rd, ws, n

	.macro	copy_u_d	ws, n

	.set	push

	.set	mips64r2

	.set	msa

	copy_u.d \rd, $w\ws[\n]

	copy_u.d $1, $w\ws[\n]

	.set	pop

	.endm



	.macro	insert_w	wd, n, rs

	.macro	insert_w	wd, n

	.set	push

	.set	mips32r2

	.set	msa

	insert.w $w\wd[\n], \rs

	insert.w $w\wd[\n], $1

	.set	pop

	.endm



	.macro	insert_d	wd, n, rs

	.macro	insert_d	wd, n

	.set	push

	.set	mips64r2

	.set	msa

	insert.d $w\wd[\n], \rs

	insert.d $w\wd[\n], $1

	.set	pop

	.endm

#else
@@ -283,7 +299,7 @@ 
	/*

	 * Temporary until all toolchains in use include MSA support.

	 */

	.macro	cfcmsa	rd, cs

	.macro	_cfcmsa	rd, cs

	.set	push

	.set	noat

	SET_HARDFLOAT
@@ -293,7 +309,7 @@ 
	.set	pop

	.endm



	.macro	ctcmsa	cd, rs

	.macro	_ctcmsa	cd, rs

	.set	push

	.set	noat

	SET_HARDFLOAT
@@ -320,44 +336,36 @@ 
	.set	pop

	.endm



	.macro	copy_u_w	rd, ws, n

	.macro	copy_u_w	ws, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	.insn

	.word	COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)

	/* move triggers an assembler bug... */

	or	\rd, $1, zero

	.set	pop

	.endm



	.macro	copy_u_d	rd, ws, n

	.macro	copy_u_d	ws, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	.insn

	.word	COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)

	/* move triggers an assembler bug... */

	or	\rd, $1, zero

	.set	pop

	.endm



	.macro	insert_w	wd, n, rs

	.macro	insert_w	wd, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	/* move triggers an assembler bug... */

	or	$1, \rs, zero

	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)

	.set	pop

	.endm



	.macro	insert_d	wd, n, rs

	.macro	insert_d	wd, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	/* move triggers an assembler bug... */

	or	$1, \rs, zero

	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)

	.set	pop

	.endm
@@ -399,7 +407,7 @@ 
	.set	push

	.set	noat

	SET_HARDFLOAT

	cfcmsa	$1, MSA_CSR

	_cfcmsa	$1, MSA_CSR

	sw	$1, THREAD_MSA_CSR(\thread)

	.set	pop

	.endm
@@ -409,7 +417,7 @@ 
	.set	noat

	SET_HARDFLOAT

	lw	$1, THREAD_MSA_CSR(\thread)

	ctcmsa	MSA_CSR, $1

	_ctcmsa	MSA_CSR, $1

	.set	pop

	ld_d	0, THREAD_FPR0, \thread

	ld_d	1, THREAD_FPR1, \thread
@@ -452,9 +460,6 @@ 
	insert_w \wd, 2

	insert_w \wd, 3

#endif

	.if	31-\wd

	msa_init_upper	(\wd+1)

	.endif

	.endm



	.macro	msa_init_all_upper
@@ -463,6 +468,37 @@ 
	SET_HARDFLOAT

	not	$1, zero

	msa_init_upper	0

	msa_init_upper	1

	msa_init_upper	2

	msa_init_upper	3

	msa_init_upper	4

	msa_init_upper	5

	msa_init_upper	6

	msa_init_upper	7

	msa_init_upper	8

	msa_init_upper	9

	msa_init_upper	10

	msa_init_upper	11

	msa_init_upper	12

	msa_init_upper	13

	msa_init_upper	14

	msa_init_upper	15

	msa_init_upper	16

	msa_init_upper	17

	msa_init_upper	18

	msa_init_upper	19

	msa_init_upper	20

	msa_init_upper	21

	msa_init_upper	22

	msa_init_upper	23

	msa_init_upper	24

	msa_init_upper	25

	msa_init_upper	26

	msa_init_upper	27

	msa_init_upper	28

	msa_init_upper	29

	msa_init_upper	30

	msa_init_upper	31

	.set	pop

	.endm

arch/mips/include/asm/fpu.h

+13 −7
Original line number Diff line number Diff line
@@ -48,6 +48,12 @@ enum fpu_mode { 
#define FPU_FR_MASK		0x1

};



#define __disable_fpu()							\

do {									\

	clear_c0_status(ST0_CU1);					\

	disable_fpu_hazard();						\

} while (0)



static inline int __enable_fpu(enum fpu_mode mode)

{

	int fr;
@@ -86,7 +92,12 @@ static inline int __enable_fpu(enum fpu_mode mode) 
		enable_fpu_hazard();



		/* check FR has the desired value */

		return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;

		if (!!(read_c0_status() & ST0_FR) == !!fr)

			return 0;



		/* unsupported FR value */

		__disable_fpu();

		return SIGFPE;



	default:

		BUG();
@@ -95,12 +106,6 @@ static inline int __enable_fpu(enum fpu_mode mode) 
	return SIGFPE;

}



#define __disable_fpu()							\

do {									\

	clear_c0_status(ST0_CU1);					\

	disable_fpu_hazard();						\

} while (0)



#define clear_fpu_owner()	clear_thread_flag(TIF_USEDFPU)



static inline int __is_fpu_owner(void)
@@ -170,6 +175,7 @@ static inline void lose_fpu(int save) 
		}

		disable_msa();

		clear_thread_flag(TIF_USEDMSA);

		__disable_fpu();

	} else if (is_fpu_owner()) {

		if (save)

			_save_fp(current);

arch/mips/include/asm/processor.h

+1 −1
Original line number Diff line number Diff line
@@ -105,7 +105,7 @@ union fpureg { 
#ifdef CONFIG_CPU_LITTLE_ENDIAN

# define FPR_IDX(width, idx)	(idx)

#else

# define FPR_IDX(width, idx)	((FPU_REG_WIDTH / (width)) - 1 - (idx))

# define FPR_IDX(width, idx)	((idx) ^ ((64 / (width)) - 1))

#endif



#define BUILD_FPR_ACCESS(width) \

arch/mips/kernel/asm-offsets.c

+0 −66
Original line number Diff line number Diff line
@@ -167,72 +167,6 @@ void output_thread_fpu_defines(void) 
	OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);

	OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);



	/* the least significant 64 bits of each FP register */

	OFFSET(THREAD_FPR0_LS64, task_struct,

	       thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR1_LS64, task_struct,

	       thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR2_LS64, task_struct,

	       thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR3_LS64, task_struct,

	       thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR4_LS64, task_struct,

	       thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR5_LS64, task_struct,

	       thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR6_LS64, task_struct,

	       thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR7_LS64, task_struct,

	       thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR8_LS64, task_struct,

	       thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR9_LS64, task_struct,

	       thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR10_LS64, task_struct,

	       thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR11_LS64, task_struct,

	       thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR12_LS64, task_struct,

	       thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR13_LS64, task_struct,

	       thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR14_LS64, task_struct,

	       thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR15_LS64, task_struct,

	       thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR16_LS64, task_struct,

	       thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR17_LS64, task_struct,

	       thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR18_LS64, task_struct,

	       thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR19_LS64, task_struct,

	       thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR20_LS64, task_struct,

	       thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR21_LS64, task_struct,

	       thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR22_LS64, task_struct,

	       thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR23_LS64, task_struct,

	       thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR24_LS64, task_struct,

	       thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR25_LS64, task_struct,

	       thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR26_LS64, task_struct,

	       thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR27_LS64, task_struct,

	       thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR28_LS64, task_struct,

	       thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR29_LS64, task_struct,

	       thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR30_LS64, task_struct,

	       thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]);

	OFFSET(THREAD_FPR31_LS64, task_struct,

	       thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);



	OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);

	OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);

	BLANK();