Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9859cd3b authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Simon Horman
Browse files

ARM: shmobile: r8a7794: Add DU0 clock 



The DU0 clock is an MSTP clock, child of the CPG ZX clock.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 6380d62a

arch/arm/boot/dts/r8a7794.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -1017,19 +1017,20 @@ 
			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;

			clocks = <&mp_clk>, <&mp_clk>,

				 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,

				 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;

				 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,

				 <&zx_clk>;

			#clock-cells = <1>;

			clock-indices = <

				R8A7794_CLK_EHCI R8A7794_CLK_HSUSB

				R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5

				R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0

				R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1

				R8A7794_CLK_SCIF0

				R8A7794_CLK_SCIF0 R8A7794_CLK_DU0

			>;

			clock-output-names =

				"ehci", "hsusb",

				"hscif2", "scif5", "scif4", "hscif1", "hscif0",

				"scif3", "scif2", "scif1", "scif0";

				"scif3", "scif2", "scif1", "scif0", "du0";

		};

		mstp8_clks: mstp8_clks@e6150990 {

			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";

include/dt-bindings/clock/r8a7794-clock.h

+1 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ 
#define R8A7794_CLK_SCIF2		19

#define R8A7794_CLK_SCIF1		20

#define R8A7794_CLK_SCIF0		21

#define R8A7794_CLK_DU0			24



/* MSTP8 */

#define R8A7794_CLK_VIN1		10