Merge "clk: qcom: Reflect the latest frequency plan updates for SDM855" into msm-next (9822b3f2) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/camcc-sdm855.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -52,7 +52,6 @@ enum {
		P_CAM_CC_PLL2_OUT_MAIN,
		P_CAM_CC_PLL3_OUT_EVEN,
		P_CAM_CC_PLL4_OUT_EVEN,
		P_CHIP_SLEEP_CLK,
		P_CORE_BI_PLL_TEST_SE,
		};

drivers/clk/qcom/gcc-sdm855.c

+9 −8

Original line number	Diff line number	Diff line
		@@ -58,6 +58,7 @@ enum {
		P_GPLL4_OUT_MAIN,
		P_GPLL5_OUT_MAIN,
		P_GPLL7_OUT_MAIN,
		P_GPLL9_OUT_MAIN,
		P_SLEEP_CLK,
		};

		@@ -188,6 +189,7 @@ static const char * const gcc_parent_names_7[] = {
		static const struct parent_map gcc_parent_map_8[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 1 },
		{ P_GPLL9_OUT_MAIN, 2 },
		{ P_GPLL4_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_EVEN, 6 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		@@ -196,6 +198,7 @@ static const struct parent_map gcc_parent_map_8[] = {
		static const char * const gcc_parent_names_8[] = {
		"bi_tcxo",
		"gpll0",
		"gpll9",
		"gpll4",
		"gpll0_out_even",
		"core_bi_pll_test_se",
		@@ -1165,7 +1168,7 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
		F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
		F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
		F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
		F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
		F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
		{ }
		};

		@@ -1178,16 +1181,15 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_sdcc2_apps_clk_src",
		.parent_names = gcc_parent_names_8,
		.num_parents = 5,
		.num_parents = 6,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 9600000,
		[VDD_LOWER] = 19200000,
		[VDD_MIN] = 19200000,
		[VDD_LOW] = 100000000,
		[VDD_LOW_L1] = 200000000},
		[VDD_LOW_L1] = 201600000},
		},
		};

		@@ -1216,10 +1218,9 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 9600000,
		[VDD_LOWER] = 19200000,
		[VDD_MIN] = 19200000,
		[VDD_LOW] = 50000000,
		[VDD_NOMINAL] = 100000000},
		[VDD_LOW_L1] = 100000000},
		},
		};

drivers/clk/qcom/npucc-sdm855.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -167,9 +167,9 @@ static const struct freq_tbl ftbl_npu_cc_cal_dp_clk_src[] = {
		F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
		F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
		F(350000000, P_NPU_CC_PLL1_OUT_EVEN, 2, 0, 0),
		F(466666667, P_NPU_CC_PLL0_OUT_EVEN, 3, 0, 0),
		F(700000000, P_NPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
		F(800000000, P_NPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
		F(400000000, P_NPU_CC_PLL0_OUT_EVEN, 3, 0, 0),
		F(600000000, P_NPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
		F(715000000, P_NPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
		{ }
		};

		@@ -192,9 +192,9 @@ static struct clk_rcg2 npu_cc_cal_dp_clk_src = {
		[VDD_MIN] = 200000000,
		[VDD_LOWER] = 300000000,
		[VDD_LOW] = 350000000,
		[VDD_LOW_L1] = 466666667,
		[VDD_NOMINAL] = 700000000,
		[VDD_HIGH] = 800000000},
		[VDD_LOW_L1] = 400000000,
		[VDD_NOMINAL] = 600000000,
		[VDD_HIGH] = 715000000},
		},
		};

drivers/clk/qcom/videocc-sdm855.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -100,8 +100,8 @@ static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
		F(225000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
		F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
		F(365000000, P_VIDEO_PLL0_OUT_MAIN, 3, 0, 0),
		F(444000000, P_VIDEO_PLL0_OUT_MAIN, 3, 0, 0),
		F(533000000, P_VIDEO_PLL0_OUT_MAIN, 3, 0, 0),
		F(432000000, P_VIDEO_PLL0_OUT_MAIN, 3, 0, 0),
		F(480000000, P_VIDEO_PLL0_OUT_MAIN, 3, 0, 0),
		{ }
		};

		@@ -125,8 +125,8 @@ static struct clk_rcg2 video_cc_iris_clk_src = {
		[VDD_LOWER] = 225000000,
		[VDD_LOW] = 300000000,
		[VDD_LOW_L1] = 365000000,
		[VDD_NOMINAL] = 444000000,
		[VDD_HIGH] = 533000000},
		[VDD_NOMINAL] = 432000000,
		[VDD_HIGH] = 480000000},
		},
		};