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Commit 97af71fa authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/gf100-/gr: split gpc state into its subunits 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c33b1e8c

drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c

+30 −11
Original line number Diff line number Diff line
@@ -382,8 +382,7 @@ nv108_grctx_pack_hub[] = { 
};



static const struct nvc0_graph_init

nv108_grctx_init_gpc_0[] = {

	{ 0x418380,   1, 0x04, 0x00000016 },

nv108_grctx_init_prop_0[] = {

	{ 0x418400,   1, 0x04, 0x38005e00 },

	{ 0x418404,   1, 0x04, 0x71e0ffff },

	{ 0x41840c,   1, 0x04, 0x00001008 },
@@ -392,11 +391,21 @@ nv108_grctx_init_gpc_0[] = { 
	{ 0x418450,   6, 0x04, 0x00000000 },

	{ 0x418468,   1, 0x04, 0x00000001 },

	{ 0x41846c,   2, 0x04, 0x00000000 },

	{}

};



static const struct nvc0_graph_init

nv108_grctx_init_gpc_unk_1[] = {

	{ 0x418600,   1, 0x04, 0x0000007f },

	{ 0x418684,   1, 0x04, 0x0000001f },

	{ 0x418700,   1, 0x04, 0x00000002 },

	{ 0x418704,   2, 0x04, 0x00000080 },

	{ 0x41870c,   2, 0x04, 0x00000000 },

	{}

};



static const struct nvc0_graph_init

nv108_grctx_init_setup_0[] = {

	{ 0x418800,   1, 0x04, 0x7006863a },

	{ 0x418808,   1, 0x04, 0x00000000 },

	{ 0x41880c,   1, 0x04, 0x00000030 },
@@ -407,10 +416,11 @@ nv108_grctx_init_gpc_0[] = { 
	{ 0x4188e0,   1, 0x04, 0x01000000 },

	{ 0x4188e8,   5, 0x04, 0x00000000 },

	{ 0x4188fc,   1, 0x04, 0x20100058 },

	{ 0x41891c,   1, 0x04, 0x00ff00ff },

	{ 0x418924,   1, 0x04, 0x00000000 },

	{ 0x418928,   1, 0x04, 0x00ffff00 },

	{ 0x41892c,   1, 0x04, 0x0000ff00 },

	{}

};



static const struct nvc0_graph_init

nv108_grctx_init_crstr_0[] = {

	{ 0x418b00,   1, 0x04, 0x0000001e },

	{ 0x418b08,   1, 0x04, 0x0a418820 },

	{ 0x418b0c,   1, 0x04, 0x062080e6 },
@@ -419,22 +429,31 @@ nv108_grctx_init_gpc_0[] = { 
	{ 0x418b18,   1, 0x04, 0x0a418820 },

	{ 0x418b1c,   1, 0x04, 0x000000e6 },

	{ 0x418bb8,   1, 0x04, 0x00000103 },

	{}

};



static const struct nvc0_graph_init

nv108_grctx_init_gpm_0[] = {

	{ 0x418c08,   1, 0x04, 0x00000001 },

	{ 0x418c10,   8, 0x04, 0x00000000 },

	{ 0x418c40,   1, 0x04, 0xffffffff },

	{ 0x418c6c,   1, 0x04, 0x00000001 },

	{ 0x418c80,   1, 0x04, 0x2020000c },

	{ 0x418c8c,   1, 0x04, 0x00000001 },

	{ 0x418d24,   1, 0x04, 0x00000000 },

	{ 0x419000,   1, 0x04, 0x00000780 },

	{ 0x419004,   2, 0x04, 0x00000000 },

	{ 0x419014,   1, 0x04, 0x00000004 },

	{}

};



static const struct nvc0_graph_pack

nv108_grctx_pack_gpc[] = {

	{ nv108_grctx_init_gpc_0 },

	{ nvc0_grctx_init_gpc_unk_0 },

	{ nv108_grctx_init_prop_0 },

	{ nv108_grctx_init_gpc_unk_1 },

	{ nv108_grctx_init_setup_0 },

	{ nvc0_grctx_init_zcull_0 },

	{ nv108_grctx_init_crstr_0 },

	{ nv108_grctx_init_gpm_0 },

	{ nvf0_grctx_init_gpc_unk_2 },

	{ nvc0_grctx_init_gcc_0 },

	{}

};

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c

+45 −3
Original line number Diff line number Diff line
@@ -762,9 +762,14 @@ nvc0_grctx_pack_hub[] = { 
	{}

};



static const struct nvc0_graph_init

nvc0_grctx_init_gpc_0[] = {

const struct nvc0_graph_init

nvc0_grctx_init_gpc_unk_0[] = {

	{ 0x418380,   1, 0x04, 0x00000016 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_prop_0[] = {

	{ 0x418400,   1, 0x04, 0x38004e00 },

	{ 0x418404,   1, 0x04, 0x71e0ffff },

	{ 0x418408,   1, 0x04, 0x00000000 },
@@ -774,6 +779,11 @@ nvc0_grctx_init_gpc_0[] = { 
	{ 0x418450,   6, 0x04, 0x00000000 },

	{ 0x418468,   1, 0x04, 0x00000001 },

	{ 0x41846c,   2, 0x04, 0x00000000 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_gpc_unk_1[] = {

	{ 0x418600,   1, 0x04, 0x0000001f },

	{ 0x418684,   1, 0x04, 0x0000000f },

	{ 0x418700,   1, 0x04, 0x00000002 },
@@ -781,6 +791,11 @@ nvc0_grctx_init_gpc_0[] = { 
	{ 0x418708,   1, 0x04, 0x00000000 },

	{ 0x41870c,   1, 0x04, 0x07c80000 },

	{ 0x418710,   1, 0x04, 0x00000000 },

	{}

};



static const struct nvc0_graph_init

nvc0_grctx_init_setup_0[] = {

	{ 0x418800,   1, 0x04, 0x0006860a },

	{ 0x418808,   3, 0x04, 0x00000000 },

	{ 0x418828,   1, 0x04, 0x00008442 },
@@ -789,10 +804,20 @@ nvc0_grctx_init_gpc_0[] = { 
	{ 0x4188e0,   1, 0x04, 0x01000000 },

	{ 0x4188e8,   5, 0x04, 0x00000000 },

	{ 0x4188fc,   1, 0x04, 0x00100000 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_zcull_0[] = {

	{ 0x41891c,   1, 0x04, 0x00ff00ff },

	{ 0x418924,   1, 0x04, 0x00000000 },

	{ 0x418928,   1, 0x04, 0x00ffff00 },

	{ 0x41892c,   1, 0x04, 0x0000ff00 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_crstr_0[] = {

	{ 0x418b00,   1, 0x04, 0x00000000 },

	{ 0x418b08,   1, 0x04, 0x0a418820 },

	{ 0x418b0c,   1, 0x04, 0x062080e6 },
@@ -801,10 +826,20 @@ nvc0_grctx_init_gpc_0[] = { 
	{ 0x418b18,   1, 0x04, 0x0a418820 },

	{ 0x418b1c,   1, 0x04, 0x000000e6 },

	{ 0x418bb8,   1, 0x04, 0x00000103 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_gpm_0[] = {

	{ 0x418c08,   1, 0x04, 0x00000001 },

	{ 0x418c10,   8, 0x04, 0x00000000 },

	{ 0x418c80,   1, 0x04, 0x20200004 },

	{ 0x418c8c,   1, 0x04, 0x00000001 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_gcc_0[] = {

	{ 0x419000,   1, 0x04, 0x00000780 },

	{ 0x419004,   2, 0x04, 0x00000000 },

	{ 0x419014,   1, 0x04, 0x00000004 },
@@ -813,7 +848,14 @@ nvc0_grctx_init_gpc_0[] = { 


const struct nvc0_graph_pack

nvc0_grctx_pack_gpc[] = {

	{ nvc0_grctx_init_gpc_0 },

	{ nvc0_grctx_init_gpc_unk_0 },

	{ nvc0_grctx_init_prop_0 },

	{ nvc0_grctx_init_gpc_unk_1 },

	{ nvc0_grctx_init_setup_0 },

	{ nvc0_grctx_init_zcull_0 },

	{ nvc0_grctx_init_crstr_0 },

	{ nvc0_grctx_init_gpm_0 },

	{ nvc0_grctx_init_gcc_0 },

	{}

};

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h

+17 −0
Original line number Diff line number Diff line
@@ -94,6 +94,13 @@ extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[]; 
extern const struct nvc0_graph_init nvc0_grctx_init_scc_0[];



extern const struct nvc0_graph_pack nvc0_grctx_pack_gpc[];

extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_0[];

extern const struct nvc0_graph_init nvc0_grctx_init_prop_0[];

extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_1[];

extern const struct nvc0_graph_init nvc0_grctx_init_zcull_0[];

extern const struct nvc0_graph_init nvc0_grctx_init_crstr_0[];

extern const struct nvc0_graph_init nvc0_grctx_init_gpm_0[];

extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[];



extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[];
@@ -101,6 +108,8 @@ extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[]; 


extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[];



extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[];



extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[];

extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[];
@@ -111,14 +120,22 @@ extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[]; 
extern const struct nvc0_graph_init nvd9_grctx_init_fe_0[];

extern const struct nvc0_graph_init nvd9_grctx_init_be_0[];



extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[];

extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[];

extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[];



extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[];

extern const struct nvc0_graph_init nve4_grctx_init_ds_0[];

extern const struct nvc0_graph_init nve4_grctx_init_scc_0[];



extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[];



extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[];



extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[];

extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[];



extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[];





#endif

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c

+14 −34
Original line number Diff line number Diff line
@@ -643,24 +643,7 @@ nvc1_grctx_pack_hub[] = { 
};



static const struct nvc0_graph_init

nvc1_grctx_init_gpc_0[] = {

	{ 0x418380,   1, 0x04, 0x00000016 },

	{ 0x418400,   1, 0x04, 0x38004e00 },

	{ 0x418404,   1, 0x04, 0x71e0ffff },

	{ 0x418408,   1, 0x04, 0x00000000 },

	{ 0x41840c,   1, 0x04, 0x00001008 },

	{ 0x418410,   1, 0x04, 0x0fff0fff },

	{ 0x418414,   1, 0x04, 0x00200fff },

	{ 0x418450,   6, 0x04, 0x00000000 },

	{ 0x418468,   1, 0x04, 0x00000001 },

	{ 0x41846c,   2, 0x04, 0x00000000 },

	{ 0x418600,   1, 0x04, 0x0000001f },

	{ 0x418684,   1, 0x04, 0x0000000f },

	{ 0x418700,   1, 0x04, 0x00000002 },

	{ 0x418704,   1, 0x04, 0x00000080 },

	{ 0x418708,   1, 0x04, 0x00000000 },

	{ 0x41870c,   1, 0x04, 0x07c80000 },

	{ 0x418710,   1, 0x04, 0x00000000 },

nvc1_grctx_init_setup_0[] = {

	{ 0x418800,   1, 0x04, 0x0006860a },

	{ 0x418808,   3, 0x04, 0x00000000 },

	{ 0x418828,   1, 0x04, 0x00008442 },
@@ -669,32 +652,29 @@ nvc1_grctx_init_gpc_0[] = { 
	{ 0x4188e0,   1, 0x04, 0x01000000 },

	{ 0x4188e8,   5, 0x04, 0x00000000 },

	{ 0x4188fc,   1, 0x04, 0x00100018 },

	{ 0x41891c,   1, 0x04, 0x00ff00ff },

	{ 0x418924,   1, 0x04, 0x00000000 },

	{ 0x418928,   1, 0x04, 0x00ffff00 },

	{ 0x41892c,   1, 0x04, 0x0000ff00 },

	{ 0x418b00,   1, 0x04, 0x00000000 },

	{ 0x418b08,   1, 0x04, 0x0a418820 },

	{ 0x418b0c,   1, 0x04, 0x062080e6 },

	{ 0x418b10,   1, 0x04, 0x020398a4 },

	{ 0x418b14,   1, 0x04, 0x0e629062 },

	{ 0x418b18,   1, 0x04, 0x0a418820 },

	{ 0x418b1c,   1, 0x04, 0x000000e6 },

	{ 0x418bb8,   1, 0x04, 0x00000103 },

	{}

};



const struct nvc0_graph_init

nvc1_grctx_init_gpm_0[] = {

	{ 0x418c08,   1, 0x04, 0x00000001 },

	{ 0x418c10,   8, 0x04, 0x00000000 },

	{ 0x418c6c,   1, 0x04, 0x00000001 },

	{ 0x418c80,   1, 0x04, 0x20200004 },

	{ 0x418c8c,   1, 0x04, 0x00000001 },

	{ 0x419000,   1, 0x04, 0x00000780 },

	{ 0x419004,   2, 0x04, 0x00000000 },

	{ 0x419014,   1, 0x04, 0x00000004 },

	{}

};



static const struct nvc0_graph_pack

nvc1_grctx_pack_gpc[] = {

	{ nvc1_grctx_init_gpc_0 },

	{ nvc0_grctx_init_gpc_unk_0 },

	{ nvc0_grctx_init_prop_0 },

	{ nvc0_grctx_init_gpc_unk_1 },

	{ nvc1_grctx_init_setup_0 },

	{ nvc0_grctx_init_zcull_0 },

	{ nvc0_grctx_init_crstr_0 },

	{ nvc1_grctx_init_gpm_0 },

	{ nvc0_grctx_init_gcc_0 },

	{}

};

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c

+9 −38
Original line number Diff line number Diff line
@@ -302,24 +302,7 @@ nvc8_grctx_pack_mthd[] = { 
};



static const struct nvc0_graph_init

nvc8_grctx_init_gpc_0[] = {

	{ 0x418380,   1, 0x04, 0x00000016 },

	{ 0x418400,   1, 0x04, 0x38004e00 },

	{ 0x418404,   1, 0x04, 0x71e0ffff },

	{ 0x418408,   1, 0x04, 0x00000000 },

	{ 0x41840c,   1, 0x04, 0x00001008 },

	{ 0x418410,   1, 0x04, 0x0fff0fff },

	{ 0x418414,   1, 0x04, 0x00200fff },

	{ 0x418450,   6, 0x04, 0x00000000 },

	{ 0x418468,   1, 0x04, 0x00000001 },

	{ 0x41846c,   2, 0x04, 0x00000000 },

	{ 0x418600,   1, 0x04, 0x0000001f },

	{ 0x418684,   1, 0x04, 0x0000000f },

	{ 0x418700,   1, 0x04, 0x00000002 },

	{ 0x418704,   1, 0x04, 0x00000080 },

	{ 0x418708,   1, 0x04, 0x00000000 },

	{ 0x41870c,   1, 0x04, 0x07c80000 },

	{ 0x418710,   1, 0x04, 0x00000000 },

nvc8_grctx_init_setup_0[] = {

	{ 0x418800,   1, 0x04, 0x0006860a },

	{ 0x418808,   3, 0x04, 0x00000000 },

	{ 0x418828,   1, 0x04, 0x00008442 },
@@ -328,31 +311,19 @@ nvc8_grctx_init_gpc_0[] = { 
	{ 0x4188e0,   1, 0x04, 0x01000000 },

	{ 0x4188e8,   5, 0x04, 0x00000000 },

	{ 0x4188fc,   1, 0x04, 0x20100000 },

	{ 0x41891c,   1, 0x04, 0x00ff00ff },

	{ 0x418924,   1, 0x04, 0x00000000 },

	{ 0x418928,   1, 0x04, 0x00ffff00 },

	{ 0x41892c,   1, 0x04, 0x0000ff00 },

	{ 0x418b00,   1, 0x04, 0x00000000 },

	{ 0x418b08,   1, 0x04, 0x0a418820 },

	{ 0x418b0c,   1, 0x04, 0x062080e6 },

	{ 0x418b10,   1, 0x04, 0x020398a4 },

	{ 0x418b14,   1, 0x04, 0x0e629062 },

	{ 0x418b18,   1, 0x04, 0x0a418820 },

	{ 0x418b1c,   1, 0x04, 0x000000e6 },

	{ 0x418bb8,   1, 0x04, 0x00000103 },

	{ 0x418c08,   1, 0x04, 0x00000001 },

	{ 0x418c10,   8, 0x04, 0x00000000 },

	{ 0x418c80,   1, 0x04, 0x20200004 },

	{ 0x418c8c,   1, 0x04, 0x00000001 },

	{ 0x419000,   1, 0x04, 0x00000780 },

	{ 0x419004,   2, 0x04, 0x00000000 },

	{ 0x419014,   1, 0x04, 0x00000004 },

	{}

};



static const struct nvc0_graph_pack

nvc8_grctx_pack_gpc[] = {

	{ nvc8_grctx_init_gpc_0 },

	{ nvc0_grctx_init_gpc_unk_0 },

	{ nvc0_grctx_init_prop_0 },

	{ nvc0_grctx_init_gpc_unk_1 },

	{ nvc8_grctx_init_setup_0 },

	{ nvc0_grctx_init_zcull_0 },

	{ nvc0_grctx_init_crstr_0 },

	{ nvc0_grctx_init_gpm_0 },

	{ nvc0_grctx_init_gcc_0 },

	{}

};