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Commit 96f90c79 authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Nicolas Pitre
Browse files

Merge the enabling by default of ARM_PATCH_PHYS_VIRT 

Conflicts:
	arch/arm/mach-msm/board-msm7x30.c
parents ad30a2bb daece596

arch/arm/Kconfig

+7 −11
Original line number Diff line number Diff line
@@ -195,7 +195,8 @@ config VECTORS_BASE 
	  The base address of exception vectors.



config ARM_PATCH_PHYS_VIRT

	bool "Patch physical to virtual translations at runtime"

	bool "Patch physical to virtual translations at runtime" if EMBEDDED

	default y

	depends on !XIP_KERNEL && MMU

	depends on !ARCH_REALVIEW || !SPARSEMEM

	help
@@ -204,16 +205,12 @@ config ARM_PATCH_PHYS_VIRT 
	  kernel in system memory.



	  This can only be used with non-XIP MMU kernels where the base

	  of physical memory is at a 16MB boundary, or theoretically 64K

	  for the MSM machine class.

	  of physical memory is at a 16MB boundary.



	  Only disable this option if you know that you do not require

	  this feature (eg, building a kernel for a single machine) and

	  you need to shrink the kernel to the minimal size.



config ARM_PATCH_PHYS_VIRT_16BIT

	def_bool y

	depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM

	help

	  This option extends the physical to virtual translation patching

	  to allow physical memory down to a theoretical minimum of 64K

	  boundaries.



source "init/Kconfig"
@@ -301,7 +298,6 @@ config ARCH_AT91 
	select ARCH_REQUIRE_GPIOLIB

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select ARM_PATCH_PHYS_VIRT if MMU

	help

	  This enables support for systems based on the Atmel AT91RM9200,

	  AT91SAM9 and AT91CAP9 processors.

arch/arm/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -128,6 +128,9 @@ textofs-$(CONFIG_PM_H1940) := 0x00108000 
ifeq ($(CONFIG_ARCH_SA1100),y)

textofs-$(CONFIG_SA1111) := 0x00208000

endif

textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000

textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000

textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000



# Machine directory name.  This list is sorted alphanumerically

# by CONFIG_* macro name.

arch/arm/include/asm/memory.h

+0 −7
Original line number Diff line number Diff line
@@ -151,7 +151,6 @@ 
 * so that all we need to do is modify the 8-bit constant field.

 */

#define __PV_BITS_31_24	0x81000000

#define __PV_BITS_23_16	0x00810000



extern unsigned long __pv_phys_offset;

#define PHYS_OFFSET __pv_phys_offset
@@ -169,9 +168,6 @@ static inline unsigned long __virt_to_phys(unsigned long x) 
{

	unsigned long t;

	__pv_stub(x, t, "add", __PV_BITS_31_24);

#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT

	__pv_stub(t, t, "add", __PV_BITS_23_16);

#endif

	return t;

}
@@ -179,9 +175,6 @@ static inline unsigned long __phys_to_virt(unsigned long x) 
{

	unsigned long t;

	__pv_stub(x, t, "sub", __PV_BITS_31_24);

#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT

	__pv_stub(t, t, "sub", __PV_BITS_23_16);

#endif

	return t;

}

#else

arch/arm/include/asm/module.h

+0 −4
Original line number Diff line number Diff line
@@ -31,11 +31,7 @@ struct mod_arch_specific { 


/* Add __virt_to_phys patching state as well */

#ifdef CONFIG_ARM_PATCH_PHYS_VIRT

#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT

#define MODULE_ARCH_VERMAGIC_P2V "p2v16 "

#else

#define MODULE_ARCH_VERMAGIC_P2V "p2v8 "

#endif

#else

#define MODULE_ARCH_VERMAGIC_P2V ""

#endif

arch/arm/kernel/head.S

+13 −48
Original line number Diff line number Diff line
@@ -488,13 +488,8 @@ __fixup_pv_table: 
	add	r5, r5, r3	@ adjust table end address

	add	r7, r7, r3	@ adjust __pv_phys_offset address

	str	r8, [r7]	@ save computed PHYS_OFFSET to __pv_phys_offset

#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT

	mov	r6, r3, lsr #24	@ constant for add/sub instructions

	teq	r3, r6, lsl #24 @ must be 16MiB aligned

#else

	mov	r6, r3, lsr #16	@ constant for add/sub instructions

	teq	r3, r6, lsl #16	@ must be 64kiB aligned

#endif

THUMB(	it	ne		@ cross section branch )

	bne	__error

	str	r6, [r7, #4]	@ save to __pv_offset
@@ -510,20 +505,8 @@ ENDPROC(__fixup_pv_table) 
	.text

__fixup_a_pv_table:

#ifdef CONFIG_THUMB2_KERNEL

#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT

	lsls	r0, r6, #24

	lsr	r6, #8

	beq	1f

	clz	r7, r0

	lsr	r0, #24

	lsl	r0, r7

	bic	r0, 0x0080

	lsrs	r7, #1

	orrcs   r0, #0x0080

	orr	r0, r0, r7, lsl #12

#endif

1:	lsls	r6, #24

	beq	4f

	lsls	r6, #24

	beq	2f

	clz	r7, r6

	lsr	r6, #24

	lsl	r6, r7
@@ -532,43 +515,25 @@ __fixup_a_pv_table: 
	orrcs	r6, #0x0080

	orr	r6, r6, r7, lsl #12

	orr	r6, #0x4000

	b	4f

2:	@ at this point the C flag is always clear

	add     r7, r3

#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT

	ldrh	ip, [r7]

	tst	ip, 0x0400	@ the i bit tells us LS or MS byte

	beq	3f

	cmp	r0, #0		@ set C flag, and ...

	biceq	ip, 0x0400	@ immediate zero value has a special encoding

	streqh	ip, [r7]	@ that requires the i bit cleared

#endif

3:	ldrh	ip, [r7, #2]

	b	2f

1:	add     r7, r3

	ldrh	ip, [r7, #2]

	and	ip, 0x8f00

	orrcc	ip, r6	@ mask in offset bits 31-24

	orrcs	ip, r0	@ mask in offset bits 23-16

	orr	ip, r6	@ mask in offset bits 31-24

	strh	ip, [r7, #2]

4:	cmp	r4, r5

2:	cmp	r4, r5

	ldrcc	r7, [r4], #4	@ use branch for delay slot

	bcc	2b

	bcc	1b

	bx	lr

#else

#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT

	and	r0, r6, #255	@ offset bits 23-16

	mov	r6, r6, lsr #8	@ offset bits 31-24

#else

	mov	r0, #0		@ just in case...

#endif

	b	3f

2:	ldr	ip, [r7, r3]

	b	2f

1:	ldr	ip, [r7, r3]

	bic	ip, ip, #0x000000ff

	tst	ip, #0x400	@ rotate shift tells us LS or MS byte

	orrne	ip, ip, r6	@ mask in offset bits 31-24

	orreq	ip, ip, r0	@ mask in offset bits 23-16

	orr	ip, ip, r6	@ mask in offset bits 31-24

	str	ip, [r7, r3]

3:	cmp	r4, r5

2:	cmp	r4, r5

	ldrcc	r7, [r4], #4	@ use branch for delay slot

	bcc	2b

	bcc	1b

	mov	pc, lr

#endif

ENDPROC(__fixup_a_pv_table)