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Commit 96d1f078 authored by Jon Hunter's avatar Jon Hunter Committed by Thierry Reding
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arm64: tegra: Add SOR power-domain for Tegra210 



Add node for SOR power-domain for Tegra210 and populate the SOR
power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are
dependent on this power-domain.

Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 19e61213

arch/arm64/boot/dts/nvidia/tegra210.dtsi

+27 −0
Original line number Original line Diff line number Diff line
@@ -34,6 +34,7 @@ 
			clock-names = "dpaux", "parent";

			clock-names = "dpaux", "parent";

			resets = <&tegra_car 207>;

			resets = <&tegra_car 207>;

			reset-names = "dpaux";

			reset-names = "dpaux";

			power-domains = <&pd_sor>;

			status = "disabled";

			status = "disabled";





			state_dpaux1_aux: pinmux-aux {

			state_dpaux1_aux: pinmux-aux {
@@ -108,6 +109,7 @@ 
			clock-names = "dsi", "lp", "parent";

			clock-names = "dsi", "lp", "parent";

			resets = <&tegra_car 48>;

			resets = <&tegra_car 48>;

			reset-names = "dsi";

			reset-names = "dsi";

			power-domains = <&pd_sor>;

			nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */

			nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */





			status = "disabled";

			status = "disabled";
@@ -137,6 +139,7 @@ 
			clock-names = "dsi", "lp", "parent";

			clock-names = "dsi", "lp", "parent";

			resets = <&tegra_car 82>;

			resets = <&tegra_car 82>;

			reset-names = "dsi";

			reset-names = "dsi";

			power-domains = <&pd_sor>;

			nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */

			nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */





			status = "disabled";

			status = "disabled";
@@ -178,6 +181,7 @@ 
			pinctrl-1 = <&state_dpaux_i2c>;

			pinctrl-1 = <&state_dpaux_i2c>;

			pinctrl-2 = <&state_dpaux_off>;

			pinctrl-2 = <&state_dpaux_off>;

			pinctrl-names = "aux", "i2c", "off";

			pinctrl-names = "aux", "i2c", "off";

			power-domains = <&pd_sor>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -197,6 +201,7 @@ 
			pinctrl-1 = <&state_dpaux1_i2c>;

			pinctrl-1 = <&state_dpaux1_i2c>;

			pinctrl-2 = <&state_dpaux1_off>;

			pinctrl-2 = <&state_dpaux1_off>;

			pinctrl-names = "aux", "i2c", "off";

			pinctrl-names = "aux", "i2c", "off";

			power-domains = <&pd_sor>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -209,6 +214,7 @@ 
			clock-names = "dpaux", "parent";

			clock-names = "dpaux", "parent";

			resets = <&tegra_car 181>;

			resets = <&tegra_car 181>;

			reset-names = "dpaux";

			reset-names = "dpaux";

			power-domains = <&pd_sor>;

			status = "disabled";

			status = "disabled";





			state_dpaux_aux: pinmux-aux {

			state_dpaux_aux: pinmux-aux {
@@ -648,6 +654,26 @@ 
				#power-domain-cells = <0>;

				#power-domain-cells = <0>;

			};

			};





			pd_sor: sor {

				clocks = <&tegra_car TEGRA210_CLK_SOR0>,

					 <&tegra_car TEGRA210_CLK_SOR1>,

					 <&tegra_car TEGRA210_CLK_CSI>,

					 <&tegra_car TEGRA210_CLK_DSIA>,

					 <&tegra_car TEGRA210_CLK_DSIB>,

					 <&tegra_car TEGRA210_CLK_DPAUX>,

					 <&tegra_car TEGRA210_CLK_DPAUX1>,

					 <&tegra_car TEGRA210_CLK_MIPI_CAL>;

				resets = <&tegra_car TEGRA210_CLK_SOR0>,

					 <&tegra_car TEGRA210_CLK_SOR1>,

					 <&tegra_car TEGRA210_CLK_CSI>,

					 <&tegra_car TEGRA210_CLK_DSIA>,

					 <&tegra_car TEGRA210_CLK_DSIB>,

					 <&tegra_car TEGRA210_CLK_DPAUX>,

					 <&tegra_car TEGRA210_CLK_DPAUX1>,

					 <&tegra_car TEGRA210_CLK_MIPI_CAL>;

				#power-domain-cells = <0>;

			};



			pd_xusbss: xusba {

			pd_xusbss: xusba {

				clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;

				clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;

				resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;

				resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
@@ -942,6 +968,7 @@ 
		reg = <0x0 0x700e3000 0x0 0x100>;

		reg = <0x0 0x700e3000 0x0 0x100>;

		clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;

		clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;

		clock-names = "mipi-cal";

		clock-names = "mipi-cal";

		power-domains = <&pd_sor>;

		#nvidia,mipi-calibrate-cells = <1>;

		#nvidia,mipi-calibrate-cells = <1>;

	};

	};