Loading drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c +1 −2 Original line number Diff line number Diff line Loading @@ -1182,9 +1182,8 @@ static unsigned long vco_7nm_recalc_rate(struct clk_hw *hw, pr_debug("dec=0x%x, frac=0x%x, outdiv=%d, vco=%llu\n", dec, frac, outdiv, vco_rate); (void)mdss_pll_resource_enable(pll, false); end: (void)mdss_pll_resource_enable(pll, false); return (unsigned long)vco_rate; } Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +20 −11 Original line number Diff line number Diff line Loading @@ -538,10 +538,9 @@ static int dsi_display_status_reg_read(struct dsi_display *display) } } exit: if (rc <= 0) { dsi_display_ctrl_irq_update(display, false); /* mask only error interrupts */ if (rc <= 0) dsi_display_mask_ctrl_error_interrupts(display); } dsi_display_cmd_engine_disable(display); done: Loading Loading @@ -3593,16 +3592,24 @@ static int _dsi_display_dev_deinit(struct dsi_display *display) } /** * dsi_display_splash_res_init() - Initialize resources for continuous splash * @display: Pointer to dsi display * dsi_display_cont_splash_config() - Initialize resources for continuous splash * @dsi_display: Pointer to dsi display * Returns: Zero on success */ static int dsi_display_splash_res_init(struct dsi_display *display) int dsi_display_cont_splash_config(void *dsi_display) { struct dsi_display *display = dsi_display; int rc = 0; /* Vote for gdsc required to read register address space */ if (!display) { pr_err("invalid input display param\n"); return -EINVAL; } mutex_lock(&display->display_lock); /* Vote for gdsc required to read register address space */ display->cont_splash_client = sde_power_client_create(display->phandle, "cont_splash_client"); rc = sde_power_resource_enable(display->phandle, Loading @@ -3610,6 +3617,7 @@ static int dsi_display_splash_res_init(struct dsi_display *display) if (rc) { pr_err("failed to vote gdsc for continuous splash, rc=%d\n", rc); mutex_unlock(&display->display_lock); return -EINVAL; } Loading @@ -3625,6 +3633,9 @@ static int dsi_display_splash_res_init(struct dsi_display *display) dsi_display_clk_mngr_update_splash_status(display->clk_mngr, display->is_cont_splash_enabled); /* Set up ctrl isr before enabling core clk */ dsi_display_ctrl_isr_configure(display, true); /* Vote for Core clk and link clk. Votes on ctrl and phy * regulator are inplicit from pre clk on callback */ Loading @@ -3645,6 +3656,7 @@ static int dsi_display_splash_res_init(struct dsi_display *display) } dsi_config_host_engine_state_for_cont_splash(display); mutex_unlock(&display->display_lock); return rc; Loading @@ -3653,6 +3665,7 @@ static int dsi_display_splash_res_init(struct dsi_display *display) DSI_ALL_CLKS, DSI_CLK_OFF); clk_manager_update: dsi_display_ctrl_isr_configure(display, false); /* Update splash status for clock manager */ dsi_display_clk_mngr_update_splash_status(display->clk_mngr, false); Loading @@ -3661,6 +3674,7 @@ static int dsi_display_splash_res_init(struct dsi_display *display) (void)sde_power_resource_enable(display->phandle, display->cont_splash_client, false); display->is_cont_splash_enabled = false; mutex_unlock(&display->display_lock); return rc; } Loading Loading @@ -4106,11 +4120,6 @@ static int dsi_display_bind(struct device *dev, } } /* Initialize resources for continuous splash */ rc = dsi_display_splash_res_init(display); if (rc) pr_err("Continuous splash resource init failed, rc=%d\n", rc); goto error; error_host_deinit: Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.h +7 −0 Original line number Diff line number Diff line Loading @@ -622,4 +622,11 @@ enum dsi_pixel_format dsi_display_get_dst_format( struct drm_connector *connector, void *display); /** * dsi_display_cont_splash_config() - initialize splash resources * @display: Handle to display * * Return: Zero on Success */ int dsi_display_cont_splash_config(void *display); #endif /* _DSI_DISPLAY_H_ */ drivers/gpu/drm/msm/sde/sde_connector.h +7 −0 Original line number Diff line number Diff line Loading @@ -292,6 +292,13 @@ struct sde_connector_ops { * Returns: Zero on success, negative error code for failures */ void (*pre_destroy)(struct drm_connector *connector, void *display); /** * cont_splash_config - initialize splash resources * @display: Pointer to private display handle * Returns: zero for success, negetive for failure */ int (*cont_splash_config)(void *display); }; /** Loading drivers/gpu/drm/msm/sde/sde_encoder.c +3 −3 Original line number Diff line number Diff line Loading @@ -3424,9 +3424,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) &pending_flush); } _sde_encoder_trigger_start(sde_enc->cur_master); /* update pending_kickoff_cnt AFTER next frame is queued in HW */ /* update pending_kickoff_cnt AFTER flush but before trigger start */ for (i = 0; i < sde_enc->num_phys_encs; i++) { struct sde_encoder_phys *phys = sde_enc->phys_encs[i]; Loading @@ -3446,6 +3444,8 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) SDE_EVTLOG_FUNC_CASE2); } } _sde_encoder_trigger_start(sde_enc->cur_master); } static void _sde_encoder_ppsplit_swap_intf_for_right_only_update( Loading Loading
drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c +1 −2 Original line number Diff line number Diff line Loading @@ -1182,9 +1182,8 @@ static unsigned long vco_7nm_recalc_rate(struct clk_hw *hw, pr_debug("dec=0x%x, frac=0x%x, outdiv=%d, vco=%llu\n", dec, frac, outdiv, vco_rate); (void)mdss_pll_resource_enable(pll, false); end: (void)mdss_pll_resource_enable(pll, false); return (unsigned long)vco_rate; } Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +20 −11 Original line number Diff line number Diff line Loading @@ -538,10 +538,9 @@ static int dsi_display_status_reg_read(struct dsi_display *display) } } exit: if (rc <= 0) { dsi_display_ctrl_irq_update(display, false); /* mask only error interrupts */ if (rc <= 0) dsi_display_mask_ctrl_error_interrupts(display); } dsi_display_cmd_engine_disable(display); done: Loading Loading @@ -3593,16 +3592,24 @@ static int _dsi_display_dev_deinit(struct dsi_display *display) } /** * dsi_display_splash_res_init() - Initialize resources for continuous splash * @display: Pointer to dsi display * dsi_display_cont_splash_config() - Initialize resources for continuous splash * @dsi_display: Pointer to dsi display * Returns: Zero on success */ static int dsi_display_splash_res_init(struct dsi_display *display) int dsi_display_cont_splash_config(void *dsi_display) { struct dsi_display *display = dsi_display; int rc = 0; /* Vote for gdsc required to read register address space */ if (!display) { pr_err("invalid input display param\n"); return -EINVAL; } mutex_lock(&display->display_lock); /* Vote for gdsc required to read register address space */ display->cont_splash_client = sde_power_client_create(display->phandle, "cont_splash_client"); rc = sde_power_resource_enable(display->phandle, Loading @@ -3610,6 +3617,7 @@ static int dsi_display_splash_res_init(struct dsi_display *display) if (rc) { pr_err("failed to vote gdsc for continuous splash, rc=%d\n", rc); mutex_unlock(&display->display_lock); return -EINVAL; } Loading @@ -3625,6 +3633,9 @@ static int dsi_display_splash_res_init(struct dsi_display *display) dsi_display_clk_mngr_update_splash_status(display->clk_mngr, display->is_cont_splash_enabled); /* Set up ctrl isr before enabling core clk */ dsi_display_ctrl_isr_configure(display, true); /* Vote for Core clk and link clk. Votes on ctrl and phy * regulator are inplicit from pre clk on callback */ Loading @@ -3645,6 +3656,7 @@ static int dsi_display_splash_res_init(struct dsi_display *display) } dsi_config_host_engine_state_for_cont_splash(display); mutex_unlock(&display->display_lock); return rc; Loading @@ -3653,6 +3665,7 @@ static int dsi_display_splash_res_init(struct dsi_display *display) DSI_ALL_CLKS, DSI_CLK_OFF); clk_manager_update: dsi_display_ctrl_isr_configure(display, false); /* Update splash status for clock manager */ dsi_display_clk_mngr_update_splash_status(display->clk_mngr, false); Loading @@ -3661,6 +3674,7 @@ static int dsi_display_splash_res_init(struct dsi_display *display) (void)sde_power_resource_enable(display->phandle, display->cont_splash_client, false); display->is_cont_splash_enabled = false; mutex_unlock(&display->display_lock); return rc; } Loading Loading @@ -4106,11 +4120,6 @@ static int dsi_display_bind(struct device *dev, } } /* Initialize resources for continuous splash */ rc = dsi_display_splash_res_init(display); if (rc) pr_err("Continuous splash resource init failed, rc=%d\n", rc); goto error; error_host_deinit: Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.h +7 −0 Original line number Diff line number Diff line Loading @@ -622,4 +622,11 @@ enum dsi_pixel_format dsi_display_get_dst_format( struct drm_connector *connector, void *display); /** * dsi_display_cont_splash_config() - initialize splash resources * @display: Handle to display * * Return: Zero on Success */ int dsi_display_cont_splash_config(void *display); #endif /* _DSI_DISPLAY_H_ */
drivers/gpu/drm/msm/sde/sde_connector.h +7 −0 Original line number Diff line number Diff line Loading @@ -292,6 +292,13 @@ struct sde_connector_ops { * Returns: Zero on success, negative error code for failures */ void (*pre_destroy)(struct drm_connector *connector, void *display); /** * cont_splash_config - initialize splash resources * @display: Pointer to private display handle * Returns: zero for success, negetive for failure */ int (*cont_splash_config)(void *display); }; /** Loading
drivers/gpu/drm/msm/sde/sde_encoder.c +3 −3 Original line number Diff line number Diff line Loading @@ -3424,9 +3424,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) &pending_flush); } _sde_encoder_trigger_start(sde_enc->cur_master); /* update pending_kickoff_cnt AFTER next frame is queued in HW */ /* update pending_kickoff_cnt AFTER flush but before trigger start */ for (i = 0; i < sde_enc->num_phys_encs; i++) { struct sde_encoder_phys *phys = sde_enc->phys_encs[i]; Loading @@ -3446,6 +3444,8 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) SDE_EVTLOG_FUNC_CASE2); } } _sde_encoder_trigger_start(sde_enc->cur_master); } static void _sde_encoder_ppsplit_swap_intf_for_right_only_update( Loading