Commit 95881a54 authored Nov 18, 2016 by Chen-Yu Tsai Committed by Maxime Ripard Nov 21, 2016

clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it



The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.

Add the 2 LDO enable bits to the gate bits. This fixes issues with
the TCON not sending vblank interrupts when the tcon and dot clock are
indirectly clocked from the PLL-MIPI clock.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent ac95330b

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -143,7 +143,7 @@ static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
		4, 2, /* K */
		0, 4, /* M */
		21, 0, /* mux */
		BIT(31), /* gate */
		BIT(31) \| BIT(23) \| BIT(22), /* gate */
		BIT(28), /* lock */
		CLK_SET_RATE_UNGATE);