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Commit 95298355 authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86: Move Nehalem PEBS code to flag 



Minor cleanup: use an explicit x86_pmu flag to handle the
missing Lock / TLB information on Nehalem, instead of always
checking the model number for each PEBS sample.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: acme@kernel.org
Cc: jolsa@kernel.org
Link: http://lkml.kernel.org/r/20170816222156.19953-2-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent d9a50b02

arch/x86/events/intel/core.c

+1 −0
Original line number Diff line number Diff line
@@ -3905,6 +3905,7 @@ __init int intel_pmu_init(void) 


		intel_pmu_pebs_data_source_nhm();

		x86_add_quirk(intel_nehalem_quirk);

		x86_pmu.pebs_no_tlb = 1;



		pr_cont("Nehalem events, ");

		break;

arch/x86/events/intel/ds.c

+1 −4
Original line number Diff line number Diff line
@@ -149,8 +149,6 @@ static u64 load_latency_data(u64 status) 
{

	union intel_x86_pebs_dse dse;

	u64 val;

	int model = boot_cpu_data.x86_model;

	int fam = boot_cpu_data.x86;



	dse.val = status;
@@ -162,8 +160,7 @@ static u64 load_latency_data(u64 status) 
	/*

	 * Nehalem models do not support TLB, Lock infos

	 */

	if (fam == 0x6 && (model == 26 || model == 30

	    || model == 31 || model == 46)) {

	if (x86_pmu.pebs_no_tlb) {

		val |= P(TLB, NA) | P(LOCK, NA);

		return val;

	}

arch/x86/events/perf_event.h

+2 −1
Original line number Diff line number Diff line
@@ -591,7 +591,8 @@ struct x86_pmu { 
			pebs		:1,

			pebs_active	:1,

			pebs_broken	:1,

			pebs_prec_dist	:1;

			pebs_prec_dist	:1,

			pebs_no_tlb	:1;

	int		pebs_record_size;

	int		pebs_buffer_size;

	void		(*drain_pebs)(struct pt_regs *regs);