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Commit 94f4efdb authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: cpu-qcs405: Update the fmax voltage for HF PLL 



The voltage requirement for the HFPLL to support 2GHz has been updated as
per the HW design recommendation.

Change-Id: I5c9f3919cd247bb0005c4902b65bbb621fee4fde
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 753e04cd

drivers/clk/qcom/clk-cpu-qcs405.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -267,8 +267,7 @@ static struct clk_pll apcs_cpu_pll = { 
		.ops = &clk_pll_hf_ops,

		.ops = &clk_pll_hf_ops,

		.vdd_class = &vdd_hf_pll,

		.vdd_class = &vdd_hf_pll,

		.rate_max = (unsigned long[VDD_HF_PLL_NUM]) {

		.rate_max = (unsigned long[VDD_HF_PLL_NUM]) {

			[VDD_HF_PLL_SVS] = 1000000000,

			[VDD_HF_PLL_SVS] = 2000000000,

			[VDD_HF_PLL_NOM] = 2000000000,

		},

		},

		.num_rate_max = VDD_HF_PLL_NUM,

		.num_rate_max = VDD_HF_PLL_NUM,

	},

	},