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Commit 949bdfed authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-fixes-for-4.12' of... 

Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Allwinner clock fixes for 4.12

Some fixes that fix some bindings that went in 4.12, fix a few reset and
clock offsets and a build error fix

* tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
parents 658a7568 d85da227

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+4 −3
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ Required properties : 
- #clock-cells : must contain 1

- #reset-cells : must contain 1



For the PRCM CCUs on H3/A64, one more clock is needed:

For the PRCM CCUs on H3/A64, two more clocks are needed:

- "pll-periph": the SoC's peripheral PLL from the main CCU

- "iosc": the SoC's internal frequency oscillator



Example for generic CCU:
@@ -39,8 +40,8 @@ Example for PRCM CCU: 
r_ccu: clock@01f01400 {

	compatible = "allwinner,sun50i-a64-r-ccu";

	reg = <0x01f01400 0x100>;

	clocks = <&osc24M>, <&osc32k>, <&iosc>;

	clock-names = "hosc", "losc", "iosc";

	clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;

	clock-names = "hosc", "losc", "iosc", "pll-periph";

	#clock-cells = <1>;

	#reset-cells = <1>;

};

drivers/clk/sunxi-ng/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ config SUN8I_R_CCU 
	bool "Support for Allwinner SoCs' PRCM CCUs"

	select SUNXI_CCU_DIV

	select SUNXI_CCU_GATE

	select SUNXI_CCU_MP

	default MACH_SUN8I || (ARCH_SUNXI && ARM64)



endif

drivers/clk/sunxi-ng/ccu-sun50i-a64.h

+3 −1
Original line number Diff line number Diff line
@@ -31,7 +31,9 @@ 
#define CLK_PLL_VIDEO0_2X		8

#define CLK_PLL_VE			9

#define CLK_PLL_DDR0			10

#define CLK_PLL_PERIPH0			11



/* PLL_PERIPH0 exported for PRCM */



#define CLK_PLL_PERIPH0_2X		12

#define CLK_PLL_PERIPH1			13

#define CLK_PLL_PERIPH1_2X		14

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

+1 −1
Original line number Diff line number Diff line
@@ -556,7 +556,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents, 
				 0x12c, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);

static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,

				 0x12c, 0, 4, 24, 3, BIT(31),

				 0x130, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);



static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",

drivers/clk/sunxi-ng/ccu-sun8i-h3.h

+3 −1
Original line number Diff line number Diff line
@@ -29,7 +29,9 @@ 
#define CLK_PLL_VIDEO		6

#define CLK_PLL_VE		7

#define CLK_PLL_DDR		8

#define CLK_PLL_PERIPH0		9



/* PLL_PERIPH0 exported for PRCM */



#define CLK_PLL_PERIPH0_2X	10

#define CLK_PLL_GPU		11

#define CLK_PLL_PERIPH1		12