Merge changes I3d47efe3,Ia064fea4,I42c889ac,I1ddba6b1,I08c83117,I0c0706ca,I1982ce7b into msm-4.14 (947c85b6) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/msm/adreno-gpulist.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -385,7 +385,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.major = 4,		.major = 4,
	.minor = 0,		.minor = 0,
	.patchid = ANY_ID,		.patchid = ANY_ID,
	.features = ADRENO_64BIT \| ADRENO_RPMH,		.features = ADRENO_64BIT \| ADRENO_RPMH \| ADRENO_GPMU,
	.sqefw_name = "a630_sqe.fw",		.sqefw_name = "a630_sqe.fw",
	.zap_name = "a640_zap",		.zap_name = "a640_zap",
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,

drivers/gpu/msm/adreno.c

+16 −30

Original line number	Original line	Diff line number	Diff line
	@@ -113,8 +113,8 @@ static struct adreno_device device_3d0 = {
	.profile.enabled = false,		.profile.enabled = false,
	.active_list = LIST_HEAD_INIT(device_3d0.active_list),		.active_list = LIST_HEAD_INIT(device_3d0.active_list),
	.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),		.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),
	.gpu_llc_slice_enable = true,		.gpu_llc_slice_enable = false,
	.gpuhtw_llc_slice_enable = true,		.gpuhtw_llc_slice_enable = false,
	.preempt = {		.preempt = {
	.preempt_level = 1,		.preempt_level = 1,
	.skipsaverestore = 1,		.skipsaverestore = 1,
	@@ -913,6 +913,18 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	struct kgsl_pwrctrl *pwr = &device->pwrctrl;		struct kgsl_pwrctrl *pwr = &device->pwrctrl;
	struct device_node *child;		struct device_node *child;
			int ret;

			/* ADD the GPU OPP table if we define it */
			if (of_find_property(device->pdev->dev.of_node,
			"operating-points-v2", NULL)) {
			ret = dev_pm_opp_of_add_table(&device->pdev->dev);
			if (ret) {
			KGSL_CORE_ERR("Unable to set the GPU OPP table: %d\n",
			ret);
			return ret;
			}
			}

	pwr->num_pwrlevels = 0;		pwr->num_pwrlevels = 0;

	@@ -1082,6 +1094,8 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev,
	if (of_property_read_u32(node, "qcom,idle-timeout", &timeout))		if (of_property_read_u32(node, "qcom,idle-timeout", &timeout))
	timeout = 80;		timeout = 80;

			/* Force disable slumber */
			timeout = 10000000;
	device->pwrctrl.interval_timeout = msecs_to_jiffies(timeout);		device->pwrctrl.interval_timeout = msecs_to_jiffies(timeout);

	device->pwrctrl.bus_control = of_property_read_bool(node,		device->pwrctrl.bus_control = of_property_read_bool(node,
	@@ -1279,29 +1293,9 @@ static int adreno_probe(struct platform_device *pdev)

	adreno_sysfs_init(adreno_dev);		adreno_sysfs_init(adreno_dev);

	kgsl_pwrscale_init(&pdev->dev, CONFIG_QCOM_ADRENO_DEFAULT_GOVERNOR);

	/* Initialize coresight for the target */		/* Initialize coresight for the target */
	adreno_coresight_init(adreno_dev);		adreno_coresight_init(adreno_dev);

	/* Get the system cache slice descriptor for GPU */
	adreno_dev->gpu_llc_slice = adreno_llc_getd(&pdev->dev, "gpu");
	if (IS_ERR(adreno_dev->gpu_llc_slice)) {
	KGSL_DRV_WARN(device,
	"Failed to get GPU LLC slice descriptor (%ld)\n",
	PTR_ERR(adreno_dev->gpu_llc_slice));
	adreno_dev->gpu_llc_slice = NULL;
	}

	/* Get the system cache slice descriptor for GPU pagetables */
	adreno_dev->gpuhtw_llc_slice = adreno_llc_getd(&pdev->dev, "gpuhtw");
	if (IS_ERR(adreno_dev->gpuhtw_llc_slice)) {
	KGSL_DRV_WARN(device,
	"Failed to get gpuhtw LLC slice descriptor (%ld)\n",
	PTR_ERR(adreno_dev->gpuhtw_llc_slice));
	adreno_dev->gpuhtw_llc_slice = NULL;
	}

	#ifdef CONFIG_INPUT		#ifdef CONFIG_INPUT
	if (!device->pwrctrl.input_disable) {		if (!device->pwrctrl.input_disable) {
	adreno_input_handler.private = device;		adreno_input_handler.private = device;
	@@ -1885,14 +1879,6 @@ static int _adreno_start(struct adreno_device *adreno_dev)
	/* Start the GPU */		/* Start the GPU */
	gpudev->start(adreno_dev);		gpudev->start(adreno_dev);

	/*
	* The system cache control registers
	* live on the CX rail. Hence need
	* reprogramming everytime the GPU
	* comes out of power collapse.
	*/
	adreno_llc_setup(device);

	/* Re-initialize the coresight registers if applicable */		/* Re-initialize the coresight registers if applicable */
	adreno_coresight_start(adreno_dev);		adreno_coresight_start(adreno_dev);

drivers/gpu/msm/adreno_a6xx.c

+0 −14

Original line number	Original line	Diff line number	Diff line
	@@ -980,7 +980,6 @@ static int a6xx_microcode_load(struct adreno_device *adreno_dev)
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	struct adreno_firmware *fw = ADRENO_FW(adreno_dev, ADRENO_FW_SQE);		struct adreno_firmware *fw = ADRENO_FW(adreno_dev, ADRENO_FW_SQE);
	uint64_t gpuaddr;		uint64_t gpuaddr;
	void *zap;
	int ret = 0;		int ret = 0;

	gpuaddr = fw->memdesc.gpuaddr;		gpuaddr = fw->memdesc.gpuaddr;
	@@ -988,19 +987,6 @@ static int a6xx_microcode_load(struct adreno_device *adreno_dev)
	lower_32_bits(gpuaddr));		lower_32_bits(gpuaddr));
	kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_HI,		kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_HI,
	upper_32_bits(gpuaddr));		upper_32_bits(gpuaddr));

	/* Load the zap shader firmware through PIL if its available */
	if (adreno_dev->gpucore->zap_name && !adreno_dev->zap_loaded) {
	zap = subsystem_get(adreno_dev->gpucore->zap_name);

	/* Return error if the zap shader cannot be loaded */
	if (IS_ERR_OR_NULL(zap)) {
	ret = (zap == NULL) ? -ENODEV : PTR_ERR(zap);
	zap = NULL;
	} else
	adreno_dev->zap_loaded = 1;
	}

	return ret;		return ret;
	}		}

drivers/gpu/msm/kgsl.c

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1059,7 +1059,6 @@ static int kgsl_close_device(struct kgsl_device *device)
	int result = 0;		int result = 0;

	mutex_lock(&device->mutex);		mutex_lock(&device->mutex);
	device->open_count--;
	if (device->open_count == 0) {		if (device->open_count == 0) {

	/* Wait for the active count to go to 0 */		/* Wait for the active count to go to 0 */
	@@ -1159,6 +1158,9 @@ static int kgsl_open_device(struct kgsl_device *device)
	complete_all(&device->hwaccess_gate);		complete_all(&device->hwaccess_gate);
	kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE);		kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE);
	kgsl_active_count_put(device);		kgsl_active_count_put(device);

			/* Do not let the device close */
			device->open_count = 1;
	}		}
	device->open_count++;		device->open_count++;
	err:		err:

drivers/gpu/msm/kgsl_gmu.c

+16 −2

Original line number	Original line	Diff line number	Diff line
	@@ -21,6 +21,7 @@
	#include <linux/pm_opp.h>		#include <linux/pm_opp.h>
	#include <linux/io.h>		#include <linux/io.h>
	#include <soc/qcom/cmd-db.h>		#include <soc/qcom/cmd-db.h>
			#include <dt-bindings/regulator/qcom,rpmh-regulator.h>

	#include "kgsl_device.h"		#include "kgsl_device.h"
	#include "kgsl_gmu.h"		#include "kgsl_gmu.h"
	@@ -836,7 +837,8 @@ static int rpmh_arc_votes_init(struct gmu_device *gmu,
	}		}

	/* Values from OPP framework are offset by 1 */		/* Values from OPP framework are offset by 1 */
	vlvl_tbl[i] = dev_pm_opp_get_voltage(opp) - 1;		vlvl_tbl[i] = dev_pm_opp_get_voltage(opp)
			- RPMH_REGULATOR_LEVEL_OFFSET;
	dev_pm_opp_put(opp);		dev_pm_opp_put(opp);
	}		}

	@@ -1063,10 +1065,22 @@ static irqreturn_t hfi_irq_handler(int irq, void *data)

	static int gmu_pwrlevel_probe(struct gmu_device gmu, struct device_node node)		static int gmu_pwrlevel_probe(struct gmu_device gmu, struct device_node node)
	{		{
			int ret;
	struct device_node pwrlevel_node, child;		struct device_node pwrlevel_node, child;

	pwrlevel_node = of_find_node_by_name(node, "qcom,gmu-pwrlevels");		/* Add the GMU OPP table if we define it */
			if (of_find_property(gmu->pdev->dev.of_node,
			"operating-points-v2", NULL)) {
			ret = dev_pm_opp_of_add_table(&gmu->pdev->dev);
			if (ret) {
			dev_err(&gmu->pdev->dev,
			"Unable to set the GMU OPP table: %d\n",
			ret);
			return ret;
			}
			}

			pwrlevel_node = of_find_node_by_name(node, "qcom,gmu-pwrlevels");
	if (pwrlevel_node == NULL) {		if (pwrlevel_node == NULL) {
	dev_err(&gmu->pdev->dev, "Unable to find 'qcom,gmu-pwrlevels'\n");		dev_err(&gmu->pdev->dev, "Unable to find 'qcom,gmu-pwrlevels'\n");
	return -EINVAL;		return -EINVAL;