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Commit 937ebbde authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman
Browse files

staging: r8188eu: Fix smatch warning in hal/HalPhyRf_8188e.c 



Smatch reported the following warning:
drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c:1876 PHY_APCalibrate_8188E() info: ignoring unreachable code.

Once the unreachable code was removed, the entire routine was removed, which
led to the warning that phy_APCalibrate_8188E() was not used. It was also deleted
along with some unused defines.

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 47380365

drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c

+0 −423
Original line number Diff line number Diff line
@@ -1276,407 +1276,6 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t) 
	}

}



/* Analog Pre-distortion calibration */

#define		APK_BB_REG_NUM	8

#define		APK_CURVE_REG_NUM 4

#define		PATH_NUM		2



static void phy_APCalibrate_8188E(struct adapter *adapt, s8 delta, bool is2t)

{

	struct hal_data_8188e	*pHalData = GET_HAL_DATA(adapt);

	struct odm_dm_struct *dm_odm = &pHalData->odmpriv;

	u32 regD[PATH_NUM];

	u32 tmpreg, index, offset,  apkbound;

	u8 path, i, pathbound = PATH_NUM;

	u32 BB_backup[APK_BB_REG_NUM];

	u32 BB_REG[APK_BB_REG_NUM] = {

		rFPGA1_TxBlock, 	rOFDM0_TRxPathEnable,

		rFPGA0_RFMOD, rOFDM0_TRMuxPar,

		rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,

		rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE	};

	u32 BB_AP_MODE[APK_BB_REG_NUM] = {

		0x00000020, 0x00a05430, 0x02040000,

		0x000800e4, 0x00204000 };

	u32 BB_normal_AP_MODE[APK_BB_REG_NUM] = {

		0x00000020, 0x00a05430, 0x02040000,

		0x000800e4, 0x22204000 };



	u32 AFE_backup[IQK_ADDA_REG_NUM];

	u32 AFE_REG[IQK_ADDA_REG_NUM] = {

		rFPGA0_XCD_SwitchControl, rBlue_Tooth,

		rRx_Wait_CCA, 	rTx_CCK_RFON,

		rTx_CCK_BBON, rTx_OFDM_RFON,

		rTx_OFDM_BBON, rTx_To_Rx,

		rTx_To_Tx, 	rRx_CCK,

		rRx_OFDM, 	rRx_Wait_RIFS,

		rRx_TO_Rx, 	rStandby,

		rSleep, 			rPMPD_ANAEN };



	u32 MAC_backup[IQK_MAC_REG_NUM];

	u32 MAC_REG[IQK_MAC_REG_NUM] = {

		REG_TXPAUSE, 	REG_BCN_CTRL,

		REG_BCN_CTRL_1, REG_GPIO_MUXCFG};



	u32 APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {

		{0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},

		{0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}

	};



	u32 APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {

		{0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /* path settings equal to path b settings */

		{0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}

	};



	u32 APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {

		{0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},

		{0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}

	};



	u32 APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {

		{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /* path settings equal to path b settings */

		{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}

	};



	u32 AFE_on_off[PATH_NUM] = {

		0x04db25a4, 0x0b1b25a4};	/* path A on path B off / path A off path B on */



	u32 APK_offset[PATH_NUM] = {

		rConfig_AntA, rConfig_AntB};



	u32 APK_normal_offset[PATH_NUM] = {

		rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};



	u32 APK_value[PATH_NUM] = {

		0x92fc0000, 0x12fc0000};



	u32 APK_normal_value[PATH_NUM] = {

		0x92680000, 0x12680000};



	s8 APK_delta_mapping[APK_BB_REG_NUM][13] = {

		{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},

		{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},

		{-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},

		{-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},

		{-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}

	};



	u32 APK_normal_setting_value_1[13] = {

		0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,

		0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,

		0x12680000, 0x00880000, 0x00880000

	};



	u32 APK_normal_setting_value_2[16] = {

		0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,

		0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,

		0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,

		0x00050006

	};



	u32 APK_result[PATH_NUM][APK_BB_REG_NUM];	/* val_1_1a, val_1_2a, val_2a, val_3a, val_4a */

	s32 BB_offset, delta_V, delta_offset;



	if (*(dm_odm->mp_mode) == 1) {

		struct mpt_context *pMptCtx = &(adapt->mppriv.MptCtx);

		pMptCtx->APK_bound[0] = 45;

		pMptCtx->APK_bound[1] = 52;

	}



	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("AP Calibration for %s\n", (is2t ? "2T2R" : "1T1R")));

	if (!is2t)

		pathbound = 1;



	/* 2 FOR NORMAL CHIP SETTINGS */



/*  Temporarily do not allow normal driver to do the following settings

 *  because these offset and value will cause RF internal PA to be

 *  unpredictably disabled by HW, such that RF Tx signal  will disappear

 *  after disable/enable card many times on 88CU. RF SD and DD have not

 *  find the root cause, so we remove these actions temporarily.

 */

	if (*(dm_odm->mp_mode) != 1)

		return;

	/* settings adjust for normal chip */

	for (index = 0; index < PATH_NUM; index++) {

		APK_offset[index] = APK_normal_offset[index];

		APK_value[index] = APK_normal_value[index];

		AFE_on_off[index] = 0x6fdb25a4;

	}



	for (index = 0; index < APK_BB_REG_NUM; index++) {

		for (path = 0; path < pathbound; path++) {

			APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];

			APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];

		}

		BB_AP_MODE[index] = BB_normal_AP_MODE[index];

	}



	apkbound = 6;



	/* save BB default value */

	for (index = 0; index < APK_BB_REG_NUM; index++) {

		if (index == 0)		/* skip */

			continue;

		BB_backup[index] = ODM_GetBBReg(dm_odm, BB_REG[index], bMaskDWord);

	}



	/* save MAC default value */

	_PHY_SaveMACRegisters(adapt, MAC_REG, MAC_backup);



	/* save AFE default value */

	_PHY_SaveADDARegisters(adapt, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);



	for (path = 0; path < pathbound; path++) {

		if (path == RF_PATH_A) {

			/* path A APK */

			/* load APK setting */

			/* path-A */

			offset = rPdp_AntA;

			for (index = 0; index < 11; index++) {

				ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

					     ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",

					     offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));

				offset += 0x04;

			}



			ODM_SetBBReg(dm_odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);



			offset = rConfig_AntA;

			for (; index < 13; index++) {

				ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

					     ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",

					     offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));

				offset += 0x04;

			}



			/* page-B1 */

			ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x40000000);



			/* path A */

			offset = rPdp_AntA;

			for (index = 0; index < 16; index++) {

				ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

					     ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",

					     offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));



				offset += 0x04;

			}

			ODM_SetBBReg(dm_odm,  rFPGA0_IQK, bMaskDWord, 0x00000000);

		} else if (path == RF_PATH_B) {

			/* path B APK */

			/* load APK setting */

			/* path-B */

			offset = rPdp_AntB;

			for (index = 0; index < 10; index++) {

				ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

					     ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",

					     offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));



				offset += 0x04;

			}

			ODM_SetBBReg(dm_odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);

			PHY_SetBBReg(adapt, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);



			offset = rConfig_AntA;

			index = 11;

			for (; index < 13; index++) { /* offset 0xb68, 0xb6c */

				ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

					     ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",

					     offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));

				offset += 0x04;

			}



			/* page-B1 */

			ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x40000000);



			/* path B */

			offset = 0xb60;

			for (index = 0; index < 16; index++) {

				ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

					     ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",

					     offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));



				offset += 0x04;

			}

			ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0);

		}



		/* save RF default value */

		regD[path] = PHY_QueryRFReg(adapt, path, RF_TXBIAS_A, bMaskDWord);



		/* Path A AFE all on, path B AFE All off or vise versa */

		for (index = 0; index < IQK_ADDA_REG_NUM; index++)

			ODM_SetBBReg(dm_odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);

		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

			     ("phy_APCalibrate_8188E() offset 0xe70 %x\n",

			     ODM_GetBBReg(dm_odm, rRx_Wait_CCA, bMaskDWord)));



		/* BB to AP mode */

		if (path == 0) {

			for (index = 0; index < APK_BB_REG_NUM; index++) {

				if (index == 0)		/* skip */

					continue;

				else if (index < 5)

				ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);

				else if (BB_REG[index] == 0x870)

					ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);

				else

					ODM_SetBBReg(dm_odm, BB_REG[index], BIT10, 0x0);

			}



			ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);

			ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);

		} else {

			/* path B */

			ODM_SetBBReg(dm_odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);

			ODM_SetBBReg(dm_odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);

		}



		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

			     ("phy_APCalibrate_8188E() offset 0x800 %x\n",

			     ODM_GetBBReg(dm_odm, 0x800, bMaskDWord)));



		/* MAC settings */

		_PHY_MACSettingCalibration(adapt, MAC_REG, MAC_backup);



		if (path == RF_PATH_A) {

			/* Path B to standby mode */

			ODM_SetRFReg(dm_odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000);

		} else {

			/* Path A to standby mode */

			ODM_SetRFReg(dm_odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000);

			ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);

			ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);

		}



		delta_offset = ((delta+14)/2);

		if (delta_offset < 0)

			delta_offset = 0;

		else if (delta_offset > 12)

			delta_offset = 12;



		/* AP calibration */

		for (index = 0; index < APK_BB_REG_NUM; index++) {

			if (index != 1)	/* only DO PA11+PAD01001, AP RF setting */

				continue;



			tmpreg = APK_RF_init_value[path][index];

			if (!dm_odm->RFCalibrateInfo.bAPKThermalMeterIgnore) {

				BB_offset = (tmpreg & 0xF0000) >> 16;



				if (!(tmpreg & BIT15)) /* sign bit 0 */

					BB_offset = -BB_offset;



				delta_V = APK_delta_mapping[index][delta_offset];



				BB_offset += delta_V;



				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

					     ("phy_APCalibrate_8188E() APK index %d tmpreg 0x%x delta_V %d delta_offset %d\n",

					     index, tmpreg, delta_V, delta_offset));



				if (BB_offset < 0) {

					tmpreg = tmpreg & (~BIT15);

					BB_offset = -BB_offset;

				} else {

					tmpreg = tmpreg | BIT15;

				}

				tmpreg = (tmpreg & 0xFFF0FFFF) | (BB_offset << 16);

			}



			ODM_SetRFReg(dm_odm, path, RF_IPA_A, bMaskDWord, 0x8992e);

			ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(adapt, path, RF_IPA_A, bMaskDWord)));

			ODM_SetRFReg(dm_odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);

			ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(adapt, path, RF_AC, bMaskDWord)));

			ODM_SetRFReg(dm_odm, path, RF_TXBIAS_A, bMaskDWord, tmpreg);

			ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(adapt, path, RF_TXBIAS_A, bMaskDWord)));

			/*  PA11+PAD01111, one shot */

			i = 0;

			do {

				ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80000000);

				ODM_SetBBReg(dm_odm, APK_offset[path], bMaskDWord, APK_value[0]);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(dm_odm, APK_offset[path], bMaskDWord)));

				ODM_delay_ms(3);

				ODM_SetBBReg(dm_odm, APK_offset[path], bMaskDWord, APK_value[1]);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(dm_odm, APK_offset[path], bMaskDWord)));



				ODM_delay_ms(20);

				ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);



				if (path == RF_PATH_A)

					tmpreg = ODM_GetBBReg(dm_odm, rAPK, 0x03E00000);

				else

					tmpreg = ODM_GetBBReg(dm_odm, rAPK, 0xF8000000);

				ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpreg));



				i++;

			} while (tmpreg > apkbound && i < 4);



			APK_result[path][index] = tmpreg;

		}

	}



	/* reload MAC default value */

	_PHY_ReloadMACRegisters(adapt, MAC_REG, MAC_backup);



	/* reload BB default value */

	for (index = 0; index < APK_BB_REG_NUM; index++) {

		if (index == 0)		/* skip */

			continue;

		ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_backup[index]);

	}



	/* reload AFE default value */

	reload_adda_reg(adapt, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);



	/* reload RF path default value */

	for (path = 0; path < pathbound; path++) {

		ODM_SetRFReg(dm_odm, path, 0xd, bMaskDWord, regD[path]);

		if (path == RF_PATH_B) {

			ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);

			ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);

		}



		/* note no index == 0 */

		if (APK_result[path][1] > 6)

			APK_result[path][1] = 6;

		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));

	}



	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("\n"));



	for (path = 0; path < pathbound; path++) {

		ODM_SetRFReg(dm_odm, path, 0x3, bMaskDWord,

			     ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));

		if (path == RF_PATH_A)

			ODM_SetRFReg(dm_odm, path, 0x4, bMaskDWord,

				     ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));

		else

			ODM_SetRFReg(dm_odm, path, 0x4, bMaskDWord,

				     ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));

		ODM_SetRFReg(dm_odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord,

			     ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));

	}



	dm_odm->RFCalibrateInfo.bAPKdone = true;



	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));

}



#define		DP_BB_REG_NUM		7

#define		DP_RF_REG_NUM		1

#define		DP_RETRY_LIMIT		10

#define		DP_PATH_NUM		2

#define		DP_DPK_NUM			3

#define		DP_DPK_VALUE_NUM	2



void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)

{

	struct hal_data_8188e	*pHalData = GET_HAL_DATA(adapt);
@@ -1867,28 +1466,6 @@ void PHY_LCCalibrate_8188E(struct adapter *adapt) 
		     ("LCK:Finish!!!interface %d\n", dm_odm->InterfaceIndex));

}



void PHY_APCalibrate_8188E(struct adapter *adapt, s8 delta)

{

	struct hal_data_8188e	*pHalData = GET_HAL_DATA(adapt);

	struct odm_dm_struct *dm_odm = &pHalData->odmpriv;



	return;

	if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))

		return;



#if FOR_BRAZIL_PRETEST != 1

	if (dm_odm->RFCalibrateInfo.bAPKdone)

#endif

		return;



	if (dm_odm->RFType == ODM_2T2R) {

		phy_APCalibrate_8188E(adapt, delta, true);

	} else {

		/*  For 88C 1T1R */

		phy_APCalibrate_8188E(adapt, delta, false);

	}

}



static void phy_setrfpathswitch_8188e(struct adapter *adapt, bool main, bool is2t)

{

	struct hal_data_8188e	*pHalData = GET_HAL_DATA(adapt);

drivers/staging/rtl8188eu/include/HalPhyRf_8188e.h

+0 −2
Original line number Diff line number Diff line
@@ -45,8 +45,6 @@ void PHY_IQCalibrate_8188E(struct adapter *Adapter, bool ReCovery); 
void PHY_LCCalibrate_8188E(struct adapter *pAdapter);



/*  AP calibrate */

void PHY_APCalibrate_8188E(struct adapter *pAdapter, s8 delta);



void PHY_DigitalPredistortion_8188E(struct adapter *pAdapter);



void _PHY_SaveADDARegisters(struct adapter *pAdapter, u32 *ADDAReg,