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Commit 92fe9eeb authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes... 

Merge changes I0d6ef03e,I9a781072,I668c8cda,I461c08c1,I3d340323,Icfb55f4c,Id804fb81,Ie7f125db,I12cad9c3,Ie6cc9a89,I3106564a,I70128a3a,Ib010b05f,Id1c04101,I0f7917cf,I1525f98b,I98bea976,I5a7d83a3 into msm-next

* changes:
  coresight-tmc-etr: Fix conditional check in TMC read
  coresight: byte-cntr: Add support for streaming interface for ETR
  coresight: abort coresight tracing on kernel crash
  coresight: tmc: Read the TMC mode register only if clk is enabled
  coresight: tmc: Fix the spinlock release in tmc etr disable function
  coresight-tmc: add support to configure flush and reset CTIs
  coresight: tmc: Add usb support for coresight
  coresight: tmc: etr: Add usb streaming support
  defconfig: sdm855: Disable Coresight configs
  coresight: tmc: Fix use after free issue with tmc read
  coresight-tmc: Re-use ETR buffer across use cases
  coresight-tmc-etr: update higher order bits of trace buffer
  coresight: tmc: Avoid NULL pointer dereference
  coresight-tmc: Avoid reading TMC buffer before enabling
  coresight: etm: Fail probe for unsupported CPUs
  coresight: add support to read cti data
  soc: qcom: Add support for QDSS bridge driver
  coresight: tgu: Add snapshot of Trigger Generation Unit
parents 8b28c68c 61105e04

Documentation/devicetree/bindings/arm/coresight.txt

+30 −0
Original line number Diff line number Diff line
@@ -40,6 +40,9 @@ its hardware characteristcs. 
		- System Trace Macrocell:

			"arm,coresight-stm", "arm,primecell"; [1]



		- Trigger Generation Unit:

			"arm,primecell";



	* reg: physical base address and length of the register

	  set(s) of the component.
@@ -84,6 +87,16 @@ its hardware characteristcs. 


	* coresight-name: unique descriptive name of the component.



* Additional required property for coresight-tgu devices:

	* tgu-steps: must be present. Indicates number of steps supported

	  by the TGU.

	* tgu-conditions: must be present. Indicates the number of conditions

	  supported by the TGU.

	* tgu-regs: must be present. Indicates the number of regs supported

	  by the TGU.

	* tgu-timer-counters: must be present. Indicates the number of timers and

	  counters available in the TGU to do a comparision.



* Optional properties for all components:

	* reg-names: names corresponding to each reg property value.

* Optional properties for ETM/PTMs:
@@ -368,5 +381,22 @@ Example: 
		};

	};

};



5. TGUs

	ipcb_tgu: tgu@6b0c000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b999>;

		reg = <0x06B0C000 0x1000>;

		reg-names = "tgu-base";

		tgu-steps = <3>;

		tgu-conditions = <4>;

		tgu-regs = <4>;

		tgu-timer-counters = <8>;



		coresight-name = "coresight-tgu-ipcb";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};

[1]. There is currently two version of STM: STM32 and STM500.  Both

have the same HW interface and as such don't need an explicit binding name.

Documentation/devicetree/bindings/arm/msm/qdss_mhi.txt

0 → 100644
+15 −0
Original line number Diff line number Diff line 
Qualcomm Technologies, Inc. QDSS bridge Driver



This device will enable routing debug data from modem

subsystem to APSS host.



Required properties:

-compatible : "qcom,qdss-mhi".

-qcom,mhi : phandle of MHI Device to connect to.



Example:

	qcom,qdss-mhi {

		compatible = "qcom,qdss-mhi";

		qcom,mhi = <&mhi_0>;

	};

arch/arm64/configs/sdm855_defconfig

+0 −4
Original line number Diff line number Diff line
@@ -429,10 +429,6 @@ CONFIG_MEMTEST=y 
CONFIG_BUG_ON_DATA_CORRUPTION=y

CONFIG_PID_IN_CONTEXTIDR=y

CONFIG_ARM64_STRICT_BREAK_BEFORE_MAKE=y

CONFIG_CORESIGHT=y

CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y

CONFIG_CORESIGHT_SOURCE_ETM4X=y

CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y

CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y

CONFIG_SECURITY=y

CONFIG_HARDENED_USERCOPY=y

arch/arm64/kernel/traps.c

+5 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ 
#include <asm/exception.h>

#include <asm/system_misc.h>

#include <asm/sysreg.h>

#include <trace/events/exception.h>



static const char *handler[]= {

	"Synchronous Abort",
@@ -411,6 +412,8 @@ void arm64_notify_segfault(struct pt_regs *regs, unsigned long addr) 


asmlinkage void __exception do_undefinstr(struct pt_regs *regs)

{

	void __user *pc = (void __user *)instruction_pointer(regs);



	/* check for AArch32 breakpoint instructions */

	if (!aarch32_break_handler(regs))

		return;
@@ -418,6 +421,8 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) 
	if (call_undef_hook(regs) == 0)

		return;



	trace_undef_instr(regs, pc);



	force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);

}

arch/arm64/mm/fault.c

+4 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
#include <asm/kryo-arm64-edac.h>



#include <acpi/ghes.h>

#include <soc/qcom/scm.h>

#include <trace/events/exception.h>



struct fault_info {

	int	(*fn)(unsigned long addr, unsigned int esr,
@@ -304,6 +306,8 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr, 
	const struct fault_info *inf;

	unsigned int lsb = 0;



	trace_user_fault(tsk, addr, esr);



	if (unhandled_signal(tsk, sig) && show_unhandled_signals_ratelimited()) {

		inf = esr_to_fault_info(esr);

		pr_info("%s[%d]: unhandled %s (%d) at 0x%08lx, esr 0x%03x",