Merge "drm/msm/dsi-staging: Update pclk calculation stored in mode" (92d87caf) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+15 −3

Original line number	Diff line number	Diff line
		@@ -40,6 +40,9 @@
		#define TO_ON_OFF(x) ((x) ? "ON" : "OFF")

		#define CEIL(x, y) (((x) + ((y)-1)) / (y))

		#define TICKS_IN_MICRO_SECOND 1000000

		/**
		* enum dsi_ctrl_driver_ops - controller driver ops
		*/
		@@ -831,6 +834,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
		int rc = 0;
		u32 num_of_lanes = 0;
		u32 bpp;
		u32 refresh_rate = TICKS_IN_MICRO_SECOND;
		u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
		byte_clk_rate;
		struct dsi_host_common_cfg *host_cfg = &config->common_config;
		@@ -853,9 +857,17 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
		num_of_lanes = split_link->lanes_per_sublink;

		if (config->bit_clk_rate_hz_override == 0) {
		if (config->panel_mode == DSI_OP_CMD_MODE) {
		h_period = DSI_H_ACTIVE_DSC(timing);
		v_period = timing->v_active;

		do_div(refresh_rate, timing->mdp_transfer_time_us);
		} else {
		h_period = DSI_H_TOTAL_DSC(timing);
		v_period = DSI_V_TOTAL(timing);
		bit_rate = h_period * v_period * timing->refresh_rate * bpp;
		refresh_rate = timing->refresh_rate;
		}
		bit_rate = h_period * v_period * refresh_rate * bpp;
		} else {
		bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;
		}

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -36,6 +36,16 @@
		value;\
		})

		#define DSI_H_ACTIVE_DSC(t) \
		({\
		u64 value;\
		if ((t)->dsc_enabled && (t)->dsc)\
		value = (t)->dsc->pclk_per_line;\
		else\
		value = (t)->h_active;\
		value;\
		})

		#define DSI_DEBUG_NAME_LEN 32
		#define display_for_each_ctrl(index, display) \
		for (index = 0; (index < (display)->ctrl_count) &&\

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+24 −5

Original line number	Diff line number	Diff line
		@@ -42,6 +42,7 @@
		#define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
		#define MAX_PANEL_JITTER 10
		#define DEFAULT_PANEL_PREFILL_LINES 25
		#define TICKS_IN_MICRO_SECOND 1000000

		enum dsi_dsc_ratio_type {
		DSC_8BPC_8BPP,
		@@ -2431,12 +2432,15 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc)


		static int dsi_panel_parse_phy_timing(struct dsi_display_mode *mode,
		struct dsi_parser_utils *utils)
		struct dsi_parser_utils *utils, enum dsi_op_mode panel_mode)
		{
		const char *data;
		u32 len, i;
		int rc = 0;
		struct dsi_display_mode_priv_info *priv_info;
		u64 h_period, v_period;
		u32 refresh_rate = TICKS_IN_MICRO_SECOND;
		struct dsi_mode_info *timing = NULL;

		priv_info = mode->priv_info;

		@@ -2456,9 +2460,24 @@ static int dsi_panel_parse_phy_timing(struct dsi_display_mode *mode,
		priv_info->phy_timing_len = len;
		};

		mode->pixel_clk_khz = (DSI_H_TOTAL_DSC(&mode->timing) *
		DSI_V_TOTAL(&mode->timing) *
		mode->timing.refresh_rate) / 1000;
		timing = &mode->timing;
		if (!timing) {
		pr_err("timing is null\n");
		return -EINVAL;
		}

		if (panel_mode == DSI_OP_CMD_MODE) {
		h_period = DSI_H_ACTIVE_DSC(timing);
		v_period = timing->v_active;
		do_div(refresh_rate, timing->mdp_transfer_time_us);
		} else {
		h_period = DSI_H_TOTAL_DSC(timing);
		v_period = DSI_V_TOTAL(timing);
		refresh_rate = timing->refresh_rate;
		}

		mode->pixel_clk_khz = (h_period * v_period * refresh_rate) / 1000;

		return rc;
		}

		@@ -3497,7 +3516,7 @@ int dsi_panel_get_mode(struct dsi_panel *panel,
		pr_err(
		"failed to parse panel jitter config, rc=%d\n", rc);

		rc = dsi_panel_parse_phy_timing(mode, utils);
		rc = dsi_panel_parse_phy_timing(mode, utils, panel->panel_mode);
		if (rc) {
		pr_err(
		"failed to parse panel phy timings, rc=%d\n", rc);

drivers/gpu/drm/msm/sde/sde_crtc.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -1390,6 +1390,11 @@ static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
		u32 disp_bitmask = 0;
		int i;

		if (!crtc \|\| !state) {
		pr_err("Invalid crtc or state\n");
		return 0;
		}

		sde_crtc = to_sde_crtc(crtc);
		crtc_state = to_sde_crtc_state(state);