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Commit 90bb3adc authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Set qcom,no-rext-present on sdxprairie"

parents 3791df31 10d3e5cd

Documentation/devicetree/bindings/usb/qcom,msm-phy.txt

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ Optional properties: 
 - reg: Address and length of the register set for the device

   Optional regs are:

        "phy_rcal_reg": register address for efuse used for rext calibration

 - qcom,no-rext-present: Set only if external REXT is not present. Default value

   is present.



Example:

	hsphy@f9200000 {

arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi

+21 −20
Original line number Diff line number Diff line
@@ -143,6 +143,7 @@ 


		resets = <&clock_gcc GCC_QUSB2PHY_BCR>;

		reset-names = "phy_reset";

		qcom,no-rext-present;

	};



	usb_qmp_phy: ssphy@ff6000 {
@@ -191,7 +192,6 @@ 
		     USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

		     USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0

		     USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0

		     USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0

		     USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
@@ -200,12 +200,13 @@ 
		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0

		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0

		     USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8 0

		     USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x8c 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xef 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb3 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xff 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x3f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xff 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xbc 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
@@ -219,9 +220,9 @@ 
		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0

		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0

		     USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

		     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0

		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0

		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0

		     USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
@@ -232,30 +233,30 @@ 
		     USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0

		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0

		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0

		     USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0

		     USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0

		     USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0

		     USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0

		     USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x00 0

		     USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0

		     USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0

		     USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0

		     USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x05 0

		     USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5 0

		     USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x00 0

		     USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x20 0

		     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x60 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x60 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x17 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0

		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0

		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0

		     USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0

		     USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0

		     USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

		     USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0

		     USB3_UNI_PCS_CDR_RESET_TIME 0x0f 0

		     USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0

		     USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0

		     USB3_UNI_PCS_EQ_CONFIG1 0x4b 0

		     USB3_UNI_PCS_EQ_CONFIG5 0x10 0

		     USB3_UNI_PCS_EQ_CONFIG1 0x0d 0

		     USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0

		     USB3_UNI_PCS_CDR_RESET_TIME 0x02 0

		     0xffffffff 0xffffffff 0x00>;



		qcom,qmp-phy-reg-offset =

drivers/usb/phy/phy-msm-snps-hs.c

+10 −2
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ struct msm_hsphy { 
	bool			suspended;

	bool			cable_connected;

	bool			dpdm_enable;

	bool			no_rext_present;



	int			*param_override_seq;

	int			param_override_seq_cnt;
@@ -466,8 +467,12 @@ static int msm_hsphy_init(struct usb_phy *uphy) 
				phy->rcal_mask, phy->phy_rcal_reg, rcal_code);

	}



	/* Use external resistor for tuning if efuse is not programmed */

	if (!rcal_code)

	/*

	 * Use external resistor value only if:

	 * a. It is present and

	 * b. efuse is not programmed.

	 */

	if (!phy->no_rext_present && !rcal_code)

		msm_usb_write_readback(phy->base, USB2PHY_USB_PHY_RTUNE_SEL,

			RTUNE_SEL, RTUNE_SEL);
@@ -792,6 +797,9 @@ static int msm_hsphy_probe(struct platform_device *pdev) 
		}

	}



	phy->no_rext_present = of_property_read_bool(dev->of_node,

					"qcom,no-rext-present");



	phy->param_override_seq_cnt = of_property_count_elems_of_size(

					dev->of_node,

					"qcom,param-override-seq",