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Commit 906f7bd8 authored by Guru Das Srinagesh's avatar Guru Das Srinagesh Committed by Umang Agrawal
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power: smb1355: Enable valley current all the time



Enable LS valley current all the time for PCL protection.
LS_Valley threshold is set to 85%.

CRs-Fixed: 2156200
Change-Id: I835eaaabaf6b5f8a4a0f8dddb04eb2b7699d63a3
Signed-off-by: default avatarGuru Das Srinagesh <gurus@codeaurora.org>
parent c0808dbe
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+23 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@
#define ANA2_BASE	0x1100
#define BATIF_BASE	0x1200
#define USBIN_BASE	0x1300
#define ANA1_BASE	0x1400
#define MISC_BASE	0x1600

#define I2C_SS_DIG_PMIC_SID_REG			(I2C_SS_DIG_BASE + 0x45)
@@ -87,6 +88,9 @@
#define EXT_BIAS_PIN_BIT			BIT(2)
#define DIE_TEMP_COMP_HYST_BIT			BIT(1)

#define ANA1_ENG_SREFGEN_CFG2_REG		(ANA1_BASE + 0xC1)
#define VALLEY_COMPARATOR_EN_BIT		BIT(0)

#define TEMP_COMP_STATUS_REG			(MISC_BASE + 0x07)
#define SKIN_TEMP_RST_HOT_BIT			BIT(6)
#define SKIN_TEMP_UB_HOT_BIT			BIT(5)
@@ -113,6 +117,9 @@
#define MISC_CUST_SDCDC_CLK_CFG_REG		(MISC_BASE + 0xA0)
#define SWITCHER_CLK_FREQ_MASK			GENMASK(3, 0)

#define MISC_CUST_SDCDC_ILIMIT_CFG_REG		(MISC_BASE + 0xA1)
#define LS_VALLEY_THRESH_PCT_BIT		BIT(3)

#define SNARL_BARK_BITE_WD_CFG_REG		(MISC_BASE + 0x53)
#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT	BIT(7)
#define SNARL_WDOG_TIMEOUT_MASK			GENMASK(6, 4)
@@ -942,6 +949,22 @@ static int smb1355_init_hw(struct smb1355 *chip)
		return rc;
	}

	/* Enable valley current comparator all the time */
	rc = smb1355_masked_write(chip, ANA1_ENG_SREFGEN_CFG2_REG,
		VALLEY_COMPARATOR_EN_BIT, VALLEY_COMPARATOR_EN_BIT);
	if (rc < 0) {
		pr_err("Couldn't enable valley current comparator rc=%d\n", rc);
		return rc;
	}

	/* Set LS_VALLEY threshold to 85% */
	rc = smb1355_masked_write(chip, MISC_CUST_SDCDC_ILIMIT_CFG_REG,
		LS_VALLEY_THRESH_PCT_BIT, LS_VALLEY_THRESH_PCT_BIT);
	if (rc < 0) {
		pr_err("Couldn't set LS valley threshold to 85pc rc=%d\n", rc);
		return rc;
	}

	rc = smb1355_tskin_sensor_config(chip);
	if (rc < 0) {
		pr_err("Couldn't configure tskin regs rc=%d\n", rc);