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Commit 8fcf2dfd authored by Vaibhav Deshu Venkatesh's avatar Vaibhav Deshu Venkatesh
Browse files

msm: vidc: Platform specific changes for video driver 



Update register addresses and some platform specific
capabilities as per SDM855 H/W and spec.

CRs-Fixed: 2170314
Change-Id: I2cb83b318523fa3d51bd6e147f40704dd1974789
Signed-off-by: default avatarVaibhav Deshu Venkatesh <vdeshuve@codeaurora.org>
parent b31361a5

Documentation/devicetree/bindings/media/video/msm-vidc.txt

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ Venus 
Required properties:

- compatible : one of:

	- "qcom,msm-vidc"

        - "qcom,sdm855-vidc" : Invokes driver specific data for SDM855.

        - "qcom,sdm845-vidc" : Invokes driver specific data for SDM845.

        - "qcom,sdm670-vidc" : Invokes driver specific data for SDM670.

drivers/media/platform/msm/vidc/msm_vidc_platform.c

+82 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -50,6 +50,19 @@ static struct msm_vidc_codec_data default_codec_data[] = { 
	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 125, 675, 320),

};



/* Update with 855 data */

static struct msm_vidc_codec_data sdm855_codec_data[] =  {

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 10, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 10, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_ENCODER, 10, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_TME, MSM_VIDC_ENCODER, 0, 540, 540),

	CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 10, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 10, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 10, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_DECODER, 10, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 10, 200, 200),

};



static struct msm_vidc_codec_data sdm845_codec_data[] =  {

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 125, 675, 320),
@@ -101,6 +114,57 @@ static struct msm_vidc_common_data default_common_data[] = { 
	},

};



static struct msm_vidc_common_data sdm855_common_data[] = {

	{

		.key = "qcom,never-unload-fw",

		.value = 1,

	},

	{

		.key = "qcom,sw-power-collapse",

		.value = 1,

	},

	{

		.key = "qcom,domain-attr-non-fatal-faults",

		.value = 1,

	},

	{

		.key = "qcom,max-secure-instances",

		.value = 5,

	},

	{

		.key = "qcom,max-hw-load",

		.value = 4147200,	/* 4096x2160@120 */

	},

	{

		.key = "qcom,max-hq-mbs-per-frame",

		.value = 8160,

	},

	{

		.key = "qcom,max-hq-frames-per-sec",

		.value = 60,

	},

	{

		.key = "qcom,max-b-frame-size",

		.value = 8160,

	},

	{

		.key = "qcom,max-b-frames-per-sec",

		.value = 60,

	},

	{

		.key = "qcom,power-collapse-delay",

		.value = 1500,

	},

	{

		.key = "qcom,hw-resp-timeout",

		.value = 1000,

	},

	{

		.key = "qcom,debug-timeout",

		.value = 0,

	},

};



static struct msm_vidc_common_data sdm845_common_data[] = {

	{

		.key = "qcom,never-unload-fw",
@@ -255,6 +319,19 @@ static struct msm_vidc_platform_data default_data = { 
	.sku_version = 0,

};



static struct msm_vidc_platform_data sdm855_data = {

	.codec_data = sdm855_codec_data,

	.codec_data_length =  ARRAY_SIZE(sdm855_codec_data),

	.common_data = sdm855_common_data,

	.common_data_length =  ARRAY_SIZE(sdm855_common_data),

	.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,

	.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,

	.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,

	.efuse_data = NULL,

	.efuse_data_length = 0,

	.sku_version = 0,

};



static struct msm_vidc_platform_data sdm845_data = {

	.codec_data = sdm845_codec_data,

	.codec_data_length =  ARRAY_SIZE(sdm845_codec_data),
@@ -282,6 +359,10 @@ static struct msm_vidc_platform_data sdm670_data = { 
};



static const struct of_device_id msm_vidc_dt_match[] = {

	{

		.compatible = "qcom,sdm855-vidc",

		.data = &sdm855_data,

	},

	{

		.compatible = "qcom,sdm845-vidc",

		.data = &sdm845_data,

drivers/media/platform/msm/vidc/venus_boot.c

+18 −39
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -35,25 +35,16 @@ 
#include "venus_boot.h"



/* VENUS WRAPPER registers */

#define VENUS_WRAPPER_VBIF_SS_SEC_CPA_START_ADDR_v1 \

				(VIDC_WRAPPER_BASE_OFFS + 0x1018)

#define VENUS_WRAPPER_VBIF_SS_SEC_CPA_END_ADDR_v1 \

				(VIDC_WRAPPER_BASE_OFFS + 0x101C)

#define VENUS_WRAPPER_VBIF_SS_SEC_FW_START_ADDR_v1 \

#define VENUS_WRAPPER_SEC_CPA_START_ADDR			\

				(VIDC_WRAPPER_BASE_OFFS + 0x1020)

#define VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR_v1 \

#define VENUS_WRAPPER_SEC_CPA_END_ADDR				\

				(VIDC_WRAPPER_BASE_OFFS + 0x1024)



#define VENUS_WRAPPER_VBIF_SS_SEC_CPA_START_ADDR_v2 \

				(VIDC_WRAPPER_BASE_OFFS + 0x1020)

#define VENUS_WRAPPER_VBIF_SS_SEC_CPA_END_ADDR_v2 \

				(VIDC_WRAPPER_BASE_OFFS + 0x1024)

#define VENUS_WRAPPER_VBIF_SS_SEC_FW_START_ADDR_v2 \

#define VENUS_WRAPPER_SEC_FW_START_ADDR				\

				(VIDC_WRAPPER_BASE_OFFS + 0x1028)

#define VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR_v2 \

#define VENUS_WRAPPER_SEC_FW_END_ADDR				\

				(VIDC_WRAPPER_BASE_OFFS + 0x102C)



#define VENUS_WRAPPER_SW_RESET	(VIDC_WRAPPER_BASE_OFFS + 0x3000)

#define VENUS_WRAPPER_A9SS_SW_RESET	(VIDC_WRAPPER_BASE_OFFS + 0x3000)



/* VENUS VBIF registers */

#define VENUS_VBIF_CLKON_FORCE_ON			BIT(0)
@@ -210,27 +201,15 @@ static int pil_venus_auth_and_reset(void) 


	if (iommu_present) {

		u32 cpa_start_addr, cpa_end_addr, fw_start_addr, fw_end_addr;

		/* Get the cpa and fw start/end addr based on Venus version */

		if (venus_data->hw_ver_major == 0x1 &&

				venus_data->hw_ver_minor <= 1) {

			cpa_start_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_CPA_START_ADDR_v1;

			cpa_end_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_CPA_END_ADDR_v1;

			fw_start_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_FW_START_ADDR_v1;

			fw_end_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR_v1;

		} else {

		/* Get the cpa and fw start/end addr */

		cpa_start_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_CPA_START_ADDR_v2;

			VENUS_WRAPPER_SEC_CPA_START_ADDR;

		cpa_end_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_CPA_END_ADDR_v2;

			VENUS_WRAPPER_SEC_CPA_END_ADDR;

		fw_start_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_FW_START_ADDR_v2;

			VENUS_WRAPPER_SEC_FW_START_ADDR;

		fw_end_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR_v2;

		}

			VENUS_WRAPPER_SEC_FW_END_ADDR;



		/* Program CPA start and end address */

		writel_relaxed(0, reg_base + cpa_start_addr);
@@ -303,7 +282,7 @@ static int pil_venus_auth_and_reset(void) 
		}

	}

	/* Bring Arm9 out of reset */

	writel_relaxed(0, reg_base + VENUS_WRAPPER_SW_RESET);

	writel_relaxed(0, reg_base + VENUS_WRAPPER_A9SS_SW_RESET);



	venus_data->is_booted = 1;

	return 0;
@@ -328,9 +307,9 @@ static int pil_venus_shutdown(void) 
		return 0;



	/* Assert the reset to ARM9 */

	reg = readl_relaxed(reg_base + VENUS_WRAPPER_SW_RESET);

	reg = readl_relaxed(reg_base + VENUS_WRAPPER_A9SS_SW_RESET);

	reg |= BIT(4);

	writel_relaxed(reg, reg_base + VENUS_WRAPPER_SW_RESET);

	writel_relaxed(reg, reg_base + VENUS_WRAPPER_A9SS_SW_RESET);



	/* Make sure reset is asserted before the mapping is removed */

	mb();

drivers/media/platform/msm/vidc/venus_hfi.c

+20 −15
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -992,8 +992,8 @@ static inline int __boot_firmware(struct venus_hfi_device *device) 


	__write_register(device, VIDC_CTRL_INIT, 0x1);

	while (!ctrl_status && count < max_tries) {

		ctrl_status = __read_register(device, VIDC_CPU_CS_SCIACMDARG0);

		if ((ctrl_status & 0xFE) == 0x4) {

		ctrl_status = __read_register(device, VIDC_CTRL_STATUS);

		if ((ctrl_status & VIDC_CTRL_ERROR_STATUS__M) == 0x4) {

			dprintk(VIDC_ERR, "invalid setting for UC_REGION\n");

			break;

		}
@@ -1423,9 +1423,9 @@ static void __setup_ucregion_memory_map(struct venus_hfi_device *device) 
	__write_register(device, VIDC_UC_REGION_ADDR,

			(u32)device->iface_q_table.align_device_addr);

	__write_register(device, VIDC_UC_REGION_SIZE, SHARED_QSIZE);

	__write_register(device, VIDC_CPU_CS_SCIACMDARG2,

	__write_register(device, VIDC_QTBL_ADDR,

			(u32)device->iface_q_table.align_device_addr);

	__write_register(device, VIDC_CPU_CS_SCIACMDARG1, 0x01);

	__write_register(device, VIDC_QTBL_INFO, 0x01);

	if (device->sfr.align_device_addr)

		__write_register(device, VIDC_SFR_ADDR,

				(u32)device->sfr.align_device_addr);
@@ -1833,8 +1833,7 @@ static void __core_clear_interrupt(struct venus_hfi_device *device) 


	if (intr_status & VIDC_WRAPPER_INTR_STATUS_A2H_BMSK ||

		intr_status & VIDC_WRAPPER_INTR_STATUS_A2HWD_BMSK ||

		intr_status &

			VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK) {

		intr_status & VIDC_CTRL_INIT_IDLE_MSG_BMSK) {

		device->intr_status |= intr_status;

		device->reg_count++;

		dprintk(VIDC_DBG,
@@ -2741,13 +2740,13 @@ static void venus_hfi_pm_handler(struct work_struct *work) 
				"Core is in bad state, Skipping power collapse\n");

		goto skip_power_off;

	}

	pc_ready = __read_register(device, VIDC_CPU_CS_SCIACMDARG0) &

		VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY;

	pc_ready = __read_register(device, VIDC_CTRL_STATUS) &

		VIDC_CTRL_STATUS_PC_READY;

	if (!pc_ready) {

		wfi_status = __read_register(device,

				VIDC_WRAPPER_CPU_STATUS);

		idle_status = __read_register(device,

				VIDC_CPU_CS_SCIACMDARG0);

				VIDC_CTRL_STATUS);

		if (!(wfi_status & BIT(0))) {

			dprintk(VIDC_WARN,

				"Skipping PC as wfi_status (%#x) bit not set\n",
@@ -2772,9 +2771,9 @@ static void venus_hfi_pm_handler(struct work_struct *work) 
			wfi_status = __read_register(device,

					VIDC_WRAPPER_CPU_STATUS);

			pc_ready = __read_register(device,

					VIDC_CPU_CS_SCIACMDARG0);

					VIDC_CTRL_STATUS);

			if ((wfi_status & BIT(0)) && (pc_ready &

				VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY))

				VIDC_CTRL_STATUS_PC_READY))

				break;

			usleep_range(150, 250);

			count++;
@@ -3343,7 +3342,7 @@ static inline int __prepare_enable_clks(struct venus_hfi_device *device) 
		dprintk(VIDC_DBG, "Clock: %s prepared and enabled\n", cl->name);

	}



	__write_register(device, VIDC_WRAPPER_CLOCK_CONFIG, 0);

	__write_register(device, VIDC_WRAPPER_CPU_CGC_DIS, 0);

	__write_register(device, VIDC_WRAPPER_CPU_CLOCK_CONFIG, 0);

	return rc;
@@ -3921,6 +3920,7 @@ static int __disable_subcaches(struct venus_hfi_device *device) 
static int __venus_power_on(struct venus_hfi_device *device)

{

	int rc = 0;

	u32 mask_val = 0;



	if (device->power_enabled)

		return 0;
@@ -3959,8 +3959,13 @@ static int __venus_power_on(struct venus_hfi_device *device) 
	 */

	__set_registers(device);



	__write_register(device, VIDC_WRAPPER_INTR_MASK,

			VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK);

	/* All interrupts should be disabled initially 0x1F6 : Reset value */

	mask_val = __read_register(device, VIDC_WRAPPER_INTR_MASK);



	/* Write 0 to unmask CPU and WD interrupts */

	mask_val &= ~(VIDC_WRAPPER_INTR_MASK_A2HWD_BMSK |

			VIDC_WRAPPER_INTR_MASK_A2HCPU_BMSK);

	__write_register(device, VIDC_WRAPPER_INTR_MASK, mask_val);

	device->intr_status = 0;

	enable_irq(device->hal_data->irq);

drivers/media/platform/msm/vidc/vidc_hfi_io.h

+38 −86
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -16,18 +16,7 @@ 


#include <linux/io.h>



#define VENUS_VCODEC_SS_CLOCK_HALT     0x0000000C

#define VENUS_VPP_CORE_SW_RESET        0x00042004

#define VENUS_VPP_CTRL_CTRL_RESET      0x00041008



#define VIDC_VBIF_BASE_OFFS			0x00080000

#define VIDC_VBIF_VERSION			(VIDC_VBIF_BASE_OFFS + 0x00)

#define VIDC_VENUS_VBIF_DDR_OUT_MAX_BURST		\

			(VIDC_VBIF_BASE_OFFS + 0xD8)

#define VIDC_VENUS_VBIF_OCMEM_OUT_MAX_BURST		\

			(VIDC_VBIF_BASE_OFFS + 0xDC)

#define VIDC_VENUS_VBIF_ROUND_ROBIN_QOS_ARB		\

			(VIDC_VBIF_BASE_OFFS + 0x124)



#define VIDC_CPU_BASE_OFFS			0x000C0000

#define VIDC_CPU_CS_BASE_OFFS		(VIDC_CPU_BASE_OFFS + 0x00012000)
@@ -60,6 +49,21 @@ 


/* HFI_VERSION_INFO */

#define VIDC_CPU_CS_SCIACMDARG3		(VIDC_CPU_CS_BASE_OFFS + 0x58)



/* VIDC_SFR_ADDR */

#define VIDC_CPU_CS_SCIBCMD		(VIDC_CPU_CS_BASE_OFFS + 0x5C)



/* VIDC_MMAP_ADDR */

#define VIDC_CPU_CS_SCIBCMDARG0		(VIDC_CPU_CS_BASE_OFFS + 0x60)



/* VIDC_UC_REGION_ADDR */

#define VIDC_CPU_CS_SCIBARG1		(VIDC_CPU_CS_BASE_OFFS + 0x64)



/* VIDC_UC_REGION_ADDR */

#define VIDC_CPU_CS_SCIBARG2		(VIDC_CPU_CS_BASE_OFFS + 0x68)



#define VIDC_CPU_CS_SCIBARG3		(VIDC_CPU_CS_BASE_OFFS + 0x6C)



#define VIDC_CPU_IC_IRQSTATUS		(VIDC_CPU_IC_BASE_OFFS + 0x00)

#define VIDC_CPU_IC_FIQSTATUS		(VIDC_CPU_IC_BASE_OFFS + 0x04)

#define VIDC_CPU_IC_RAWINTR			(VIDC_CPU_IC_BASE_OFFS + 0x08)
@@ -95,8 +99,6 @@ 
#define VIDC_WRAPPER_INTR_MASK		(VIDC_WRAPPER_BASE_OFFS + 0x10)

#define VIDC_WRAPPER_INTR_MASK_A2HWD_BMSK	0x10

#define VIDC_WRAPPER_INTR_MASK_A2HWD_SHFT	0x4

#define VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK	0x8

#define VIDC_WRAPPER_INTR_MASK_A2HVCODEC_SHFT	0x3

#define VIDC_WRAPPER_INTR_MASK_A2HCPU_BMSK	0x4

#define VIDC_WRAPPER_INTR_MASK_A2HCPU_SHFT	0x2
@@ -106,41 +108,10 @@ 
#define VIDC_WRAPPER_INTR_CLEAR_A2H_BMSK	0x4

#define VIDC_WRAPPER_INTR_CLEAR_A2H_SHFT	0x2



#define VIDC_WRAPPER_VBIF_XIN_SW_RESET	(VIDC_WRAPPER_BASE_OFFS + 0x18)

#define VIDC_WRAPPER_VBIF_XIN_STATUS	(VIDC_WRAPPER_BASE_OFFS + 0x1C)

#define VIDC_WRAPPER_CPU_CLOCK_CONFIG	(VIDC_WRAPPER_BASE_OFFS + 0x2000)

#define VIDC_WRAPPER_VBIF_XIN_CPU_SW_RESET	\

				(VIDC_WRAPPER_BASE_OFFS + 0x2004)

#define VIDC_WRAPPER_AXI_HALT		(VIDC_WRAPPER_BASE_OFFS + 0x2008)

#define VIDC_WRAPPER_AXI_HALT_STATUS	(VIDC_WRAPPER_BASE_OFFS + 0x200C)

#define VIDC_WRAPPER_CPU_CGC_DIS	(VIDC_WRAPPER_BASE_OFFS + 0x2010)

#define VIDC_WRAPPER_CPU_STATUS (VIDC_WRAPPER_BASE_OFFS + 0x2014)

#define VIDC_VENUS_VBIF_CLK_ON		(VIDC_VBIF_BASE_OFFS + 0x4)

#define VIDC_VBIF_IN_RD_LIM_CONF0       (VIDC_VBIF_BASE_OFFS + 0xB0)

#define VIDC_VBIF_IN_RD_LIM_CONF1       (VIDC_VBIF_BASE_OFFS + 0xB4)

#define VIDC_VBIF_IN_RD_LIM_CONF2       (VIDC_VBIF_BASE_OFFS + 0xB8)

#define VIDC_VBIF_IN_RD_LIM_CONF3       (VIDC_VBIF_BASE_OFFS + 0xBC)

#define VIDC_VBIF_IN_WR_LIM_CONF0       (VIDC_VBIF_BASE_OFFS + 0xC0)

#define VIDC_VBIF_IN_WR_LIM_CONF1       (VIDC_VBIF_BASE_OFFS + 0xC4)

#define VIDC_VBIF_IN_WR_LIM_CONF2       (VIDC_VBIF_BASE_OFFS + 0xC8)

#define VIDC_VBIF_IN_WR_LIM_CONF3       (VIDC_VBIF_BASE_OFFS + 0xCC)

#define VIDC_VBIF_OUT_RD_LIM_CONF0      (VIDC_VBIF_BASE_OFFS + 0xD0)

#define VIDC_VBIF_OUT_WR_LIM_CONF0      (VIDC_VBIF_BASE_OFFS + 0xD4)

#define VIDC_VBIF_DDR_OUT_MAX_BURST     (VIDC_VBIF_BASE_OFFS + 0xD8)

#define VIDC_VBIF_OCMEM_OUT_MAX_BURST   (VIDC_VBIF_BASE_OFFS + 0xDC)

#define VIDC_VBIF_DDR_ARB_CONF0         (VIDC_VBIF_BASE_OFFS + 0xF4)

#define VIDC_VBIF_DDR_ARB_CONF1         (VIDC_VBIF_BASE_OFFS + 0xF8)

#define VIDC_VBIF_ROUND_ROBIN_QOS_ARB   (VIDC_VBIF_BASE_OFFS + 0x124)

#define VIDC_VBIF_OUT_AXI_AOOO_EN       (VIDC_VBIF_BASE_OFFS + 0x178)

#define VIDC_VBIF_OUT_AXI_AOOO          (VIDC_VBIF_BASE_OFFS + 0x17C)

#define VIDC_VBIF_ARB_CTL               (VIDC_VBIF_BASE_OFFS + 0xF0)

#define VIDC_VBIF_OUT_AXI_AMEMTYPE_CONF0 (VIDC_VBIF_BASE_OFFS + 0x160)

#define VIDC_VBIF_OUT_AXI_AMEMTYPE_CONF1 (VIDC_VBIF_BASE_OFFS + 0x164)

#define VIDC_VBIF_ADDR_TRANS_EN         (VIDC_VBIF_BASE_OFFS + 0xC00)

#define VIDC_VBIF_AT_OLD_BASE           (VIDC_VBIF_BASE_OFFS + 0xC04)

#define VIDC_VBIF_AT_OLD_HIGH           (VIDC_VBIF_BASE_OFFS + 0xC08)

#define VIDC_VBIF_AT_NEW_BASE           (VIDC_VBIF_BASE_OFFS + 0xC10)

#define VIDC_VBIF_AT_NEW_HIGH           (VIDC_VBIF_BASE_OFFS + 0xC18)

#define VENUS_VBIF_AXI_HALT_CTRL0   (VIDC_VBIF_BASE_OFFS + 0x208)

#define VENUS_VBIF_AXI_HALT_CTRL1   (VIDC_VBIF_BASE_OFFS + 0x20C)
@@ -148,47 +119,28 @@ 
#define VENUS_VBIF_AXI_HALT_CTRL1_HALT_ACK		BIT(0)

#define VENUS_VBIF_AXI_HALT_ACK_TIMEOUT_US		500000



#define VIDC_VENUS0_WRAPPER_VBIF_REQ_PRIORITY \

	(VIDC_WRAPPER_BASE_OFFS + 0x20)

#define VIDC_VENUS0_WRAPPER_VBIF_PRIORITY_LEVEL \

	(VIDC_WRAPPER_BASE_OFFS + 0x24)



#define VIDC_CTRL_INIT 0x000D2048

#define VIDC_CTRL_INIT_RESERVED_BITS31_1__M 0xFFFFFFFE

#define VIDC_CTRL_INIT_RESERVED_BITS31_1__S 1

#define VIDC_CTRL_INIT_CTRL__M 0x00000001

#define VIDC_CTRL_INIT_CTRL__S 0



#define VIDC_CTRL_STATUS 0x000D204C

#define VIDC_CTRL_STATUS_RESERVED_BITS31_8__M 0xFFFFFF00

#define VIDC_CTRL_STATUS_RESERVED_BITS31_8__S 8

#define VIDC_CTRL_ERROR_STATUS__M             0x000000FE

#define VIDC_CTRL_ERROR_STATUS__S             1

#define VIDC_CTRL_INIT_STATUS__M              0x00000001

#define VIDC_CTRL_INIT_STATUS__S              0



#define VIDC_QTBL_INFO 0x000D2050

#define VIDC_QTBL_HOSTID__M 0xFF000000

#define VIDC_QTBL_HOSTID__S 24

#define VIDC_QTBL_INFO_RESERVED_BITS23_8__M 0x00FFFF00

#define VIDC_QTBL_INFO_RESERVED_BITS23_8__S 8

#define VIDC_QTBL_STATUS__M 0x000000FF

#define VIDC_QTBL_STATUS__S 0



#define VIDC_QTBL_ADDR 0x000D2054



#define VIDC_VERSION_INFO 0x000D2058

#define VIDC_VERSION_INFO_MAJOR__M  0xF0000000

#define VIDC_VERSION_INFO_MAJOR__S  28

#define VIDC_VERSION_INFO_MINOR__M  0x0FFFFFE0

#define VIDC_VERSION_INFO_MINOR__S  5

#define VIDC_VERSION_INFO_BRANCH__M 0x0000001F

#define VIDC_VERSION_INFO_BRANCH__S 0



#define VIDC_SFR_ADDR 0x000D205C

#define VIDC_MMAP_ADDR 0x000D2060

#define VIDC_UC_REGION_ADDR 0x000D2064

#define VIDC_UC_REGION_SIZE 0x000D2068



#define VIDC_CTRL_INIT		VIDC_CPU_CS_SCIACMD



#define VIDC_CTRL_STATUS	VIDC_CPU_CS_SCIACMDARG0

#define VIDC_CTRL_ERROR_STATUS__M \

		VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK

#define VIDC_CTRL_INIT_IDLE_MSG_BMSK \

		VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK

#define VIDC_CTRL_STATUS_PC_READY \

		VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY





#define VIDC_QTBL_INFO		VIDC_CPU_CS_SCIACMDARG1



#define VIDC_QTBL_ADDR		VIDC_CPU_CS_SCIACMDARG2



#define VIDC_VERSION_INFO	VIDC_CPU_CS_SCIACMDARG3



#define VIDC_SFR_ADDR		VIDC_CPU_CS_SCIBCMD

#define VIDC_MMAP_ADDR		VIDC_CPU_CS_SCIBCMDARG0

#define VIDC_UC_REGION_ADDR	VIDC_CPU_CS_SCIBARG1

#define VIDC_UC_REGION_SIZE	VIDC_CPU_CS_SCIBARG2



/*

 * --------------------------------------------------------------------------