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Commit 8faf2e6c authored by Ben Hutchings's avatar Ben Hutchings Committed by Ralf Baechle
Browse files

MIPS: Set io_map_base for several PCI bridges lacking it 



Several MIPS platforms don't set pci_controller::io_map_base for their
PCI bridges.  This results in a panic in pci_iomap().  (The panic is
conditional on CONFIG_PCI_DOMAINS, but that is now enabled for all PCI
MIPS systems.)

Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
Cc: linux-mips@linux-mips.org
Cc: Martin Michlmayr <tbm@cyrius.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: 584784@bugs.debian.org
Patchwork: https://patchwork.linux-mips.org/patch/1377/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 0d5977d6

arch/mips/mti-malta/malta-pci.c

+2 −0
Original line number Diff line number Diff line
@@ -247,6 +247,8 @@ void __init mips_pcibios_init(void) 
	iomem_resource.end &= 0xfffffffffULL;			/* 64 GB */

	ioport_resource.end = controller->io_resource->end;



	controller->io_map_base = mips_io_port_base;



	register_pci_controller(controller);

}

arch/mips/nxp/pnx8550/common/pci.c

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ extern struct pci_ops pnx8550_pci_ops; 


static struct pci_controller pnx8550_controller = {

	.pci_ops	= &pnx8550_pci_ops,

	.io_map_base	= PNX8550_PORT_BASE,

	.io_resource	= &pci_io_resource,

	.mem_resource	= &pci_mem_resource,

};

arch/mips/nxp/pnx8550/common/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ void __init plat_mem_setup(void) 
	PNX8550_GLB2_ENAB_INTA_O = 0;



	/* IO/MEM resources. */

	set_io_port_base(KSEG1);

	set_io_port_base(PNX8550_PORT_BASE);

	ioport_resource.start = 0;

	ioport_resource.end = ~0;

	iomem_resource.start = 0;

arch/mips/pci/ops-pmcmsp.c

+1 −0
Original line number Diff line number Diff line
@@ -944,6 +944,7 @@ static struct pci_controller msp_pci_controller = { 
	.pci_ops	= &msp_pci_ops,

	.mem_resource	= &pci_mem_resource,

	.mem_offset	= 0,

	.io_map_base	= MSP_PCI_IOSPACE_BASE,

	.io_resource	= &pci_io_resource,

	.io_offset	= 0

};

arch/mips/pci/pci-yosemite.c

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ static int __init pmc_yosemite_setup(void) 
		panic(ioremap_failed);



	set_io_port_base(io_v_base);

	py_controller.io_map_base = io_v_base;

	TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);



	ioport_resource.end = TITAN_IO_SIZE - 1;