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Commit 8efaf5ed authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
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clk: imx: increase AXI clock rate to 264MHz for i.MX6UL 



On i.MX6UL, AXI clock rate's design target is 264MHz, but by default
it is only set to 198MHz which is NOT good enough for performance,
this patch increases AXI clock rate from 198MHz to 264MHz to meet
the design target, this is done by switching its parent clock
"periph" from 396MHz PFD to 528MHz PLL.

Signed-off-by: default avatarAnson Huang <b20788@freescale.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 6ff33f39

drivers/clk/imx/clk-imx6ul.c

+18 −0
Original line number Original line Diff line number Diff line
@@ -407,6 +407,24 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clk_data.clk_num = ARRAY_SIZE(clks);

	clk_data.clk_num = ARRAY_SIZE(clks);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);





	/*

	 * Lower the AHB clock rate before changing the parent clock source,

	 * as AHB clock rate can NOT be higher than 133MHz, but its parent

	 * will be switched from 396MHz PFD to 528MHz PLL in order to increase

	 * AXI clock rate, so we need to lower AHB rate first to make sure at

	 * any time, AHB rate is <= 133MHz.

	 */

	clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);



	/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */

	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);

	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);

	clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);

	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);



	/* Make sure AHB rate is 132MHz  */

	clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000);



	/* set perclk to from OSC */

	/* set perclk to from OSC */

	clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]);

	clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]);