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Commit 8e5ebd46 authored by Tharun Kumar Merugu's avatar Tharun Kumar Merugu
Browse files

adsprpc: Remove DMA cache coherency in qcs405 



qcs405 does not support DMA cache coherency, so remove
dma-cohrent property from fastrpc context banks.

Change-Id: Iac89d96590e9d7efaba2a444bf80f43d004f05ec
Acked-by: default avatarChenna Kesava Raju <chennak@qti.qualcomm.com>
Signed-off-by: default avatarTharun Kumar Merugu <mtharu@codeaurora.org>
parent b8f54403

arch/arm64/boot/dts/qcom/qcs405.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -617,48 +617,41 @@ 
			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1001 0x0>;

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb2 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1002 0x0>;

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb3 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1003 0x0>;

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb4 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1004 0x0>;

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb5 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1005 0x0>;

			dma-coherent;

		};

		qcom,msm_fastrpc_compute_cb6 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x804 0x0>;

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb7 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x805 0x0>;

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb8 {
@@ -666,7 +659,6 @@ 
			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x806 0x0>;

			shared-cb = <5>;

			dma-coherent;

		};

	};