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Commit 8e2f9d89 authored by Rama Aparna Mallavarapu's avatar Rama Aparna Mallavarapu
Browse files

coresight: tmc: Change ETR DDR transaction configuration 



Set AXI control register on ETR to use normal non-cacheable
bufferable mode to meet bandwidth requirement. There is a
disconnect between the AXI protocol version on ETR versus the
rest of the system. The below table illustrates the correct
config to be used
-----------------------------------------------------------------
ARCACHE[1:0] | AWCACHE[1:0] | Memorytype
          00 |           00 | Device Non-bufferable
          01 |           01 | Device Bufferable
          10 |           10 | Normal Non-cacheable Non-bufferable
          11 |           11 | Normal Non-cacheable Bufferable
----------------------------------------------------------------

Change-Id: I0c2255389641ede80702415b4083bfc9a46881be
Signed-off-by: default avatarSatyajit Desai <sadesai@codeaurora.org>
Signed-off-by: default avatarRama Aparna Mallavarapu <aparnam@codeaurora.org>
parent 8394c49d

drivers/hwtracing/coresight/coresight-tmc-etr.c

+3 −0
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) 
		axictl |= TMC_AXICTL_ARCACHE_OS;

	}



	axictl = (axictl &

		  ~(TMC_AXICTL_CACHE_CTL_B0 | TMC_AXICTL_CACHE_CTL_B1)) |

		  TMC_AXICTL_CACHE_CTL_B0 | TMC_AXICTL_CACHE_CTL_B1;

	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);

	tmc_write_dba(drvdata, drvdata->paddr);

	/*

drivers/hwtracing/coresight/coresight-tmc.h

+2 −0
Original line number Diff line number Diff line
@@ -74,6 +74,8 @@ 


#define TMC_AXICTL_PROT_CTL_B0	BIT(0)

#define TMC_AXICTL_PROT_CTL_B1	BIT(1)

#define TMC_AXICTL_CACHE_CTL_B0	BIT(2)

#define TMC_AXICTL_CACHE_CTL_B1	BIT(3)

#define TMC_AXICTL_SCT_GAT_MODE	BIT(7)

#define TMC_AXICTL_WR_BURST_16	0xF00

/* Write-back Read and Write-allocate */