ARM:dts:msm:Disable DCC clock for qcs405



Disable DCC clocks during DCC is probing. It's for
fixing its abnormal reset.

Change-Id: I87535063089d6a95bb07bbf131b37a1e13130721
Signed-off-by: Jinfa Wang <jinfaw@codeaurora.org>

parent 9c7152a7

arch/arm64/boot/dts/qcom/qcs405.dtsi

+0 −5

Original line number	Diff line number	Diff line
		@@ -418,11 +418,6 @@
		reg = <0x000b2000 0x1000>,
		<0x000bfc00 0x400>;

		clk-enable;
		clocks = <&clock_gcc GCC_DCC_CLK>,
		<&clock_gcc GCC_DCC_XO_CLK>;
		clock-names = "dcc_clk", "dcc_xo_clk";

		reg-names = "dcc-base", "dcc-ram-base";
		dcc-ram-offset = <0x400>;
		qcom,curr-link-list = <1>;