Loading AndroidKernel.mk +4 −0 Original line number Diff line number Diff line Loading @@ -28,6 +28,10 @@ $(warning Forcing kernel header generation only for '$(TARGET_KERNEL_HEADER_ARCH KERNEL_HEADER_ARCH := $(TARGET_KERNEL_HEADER_ARCH) endif ifeq ($(shell echo $(KERNEL_DEFCONFIG) | grep vendor),) KERNEL_DEFCONFIG := vendor/$(KERNEL_DEFCONFIG) endif KERNEL_HEADER_DEFCONFIG := $(strip $(KERNEL_HEADER_DEFCONFIG)) ifeq ($(KERNEL_HEADER_DEFCONFIG),) KERNEL_HEADER_DEFCONFIG := $(KERNEL_DEFCONFIG) Loading Documentation/devicetree/bindings/clock/qcom,gpucc.txt +2 −1 Original line number Diff line number Diff line Loading @@ -5,7 +5,8 @@ Required properties : - compatible : shall contain one of the following: "qcom,gpucc-sm8150", "qcom,gpucc-sdmshrike", "qcom,gpucc-sm6150". "qcom,gpucc-sm6150", "qcom,gpucc-sdmmagpie". - reg : shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. Loading Documentation/devicetree/bindings/firmware/qcom,scm.txt +25 −0 Original line number Diff line number Diff line Loading @@ -12,6 +12,8 @@ Required properties: * "qcom,scm-msm8690" for MSM8690 platforms * "qcom,scm-msm8996" for MSM8996 platforms * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) * "android,firmware" for firmware image * "android,vbmeta" for setting system properties for verified boot. - clocks: One to three clocks may be required based on compatible. * No clock required for "qcom,scm-msm8996" * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" Loading @@ -28,3 +30,26 @@ Example for MSM8916: clock-names = "core", "bus", "iface"; }; }; Example for SM6150: firmware: firmware { android { compatible = "android,firmware"; vbmeta { compatible = "android,vbmeta"; parts = "vbmeta,boot,system,vendor,dtbo"; }; fstab { compatible = "android,fstab"; vendor { compatible = "android,vendor"; dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,slotselect,avb"; status = "ok"; }; }; }; }; Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt +6 −1 Original line number Diff line number Diff line Loading @@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. GPU powerlevels Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins) can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a voltage, bus, and bandwitdh level. voltage, bus, bandwidth level, and a DVM value. - qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets Loading @@ -28,3 +28,8 @@ Properties: settings) - qcom,bus-min Minimum bus level to set for the power level - qcom,bus-max maximum bus level to set for the power level - qcom,dvm-val: Value that is used as a register setting for the ACD power feature. It helps determine the threshold for when ACD activates. 0xFFFFFFFF is the default value, and the setting where ACD will never activate. Documentation/devicetree/bindings/input/qti-haptics.txt +9 −0 Original line number Diff line number Diff line Loading @@ -130,6 +130,15 @@ waveforms/effects: [5:1]: waveform amplitude [0]: reserved. - qcom,wf-vmax-mv Usage: optional Value type: <u32> Definition: Specifies the maximum allowed output voltage in millivolts for this effect. Value specified here will be rounded off to the closest multiple of 116 mV. Allowed values: 0 to 3596. If this is not specified, the value defined in "qcom,vmax-mv" will be applied. - qcom,wf-play-rate-us Usage: optional Value type: <u32> Loading Loading
AndroidKernel.mk +4 −0 Original line number Diff line number Diff line Loading @@ -28,6 +28,10 @@ $(warning Forcing kernel header generation only for '$(TARGET_KERNEL_HEADER_ARCH KERNEL_HEADER_ARCH := $(TARGET_KERNEL_HEADER_ARCH) endif ifeq ($(shell echo $(KERNEL_DEFCONFIG) | grep vendor),) KERNEL_DEFCONFIG := vendor/$(KERNEL_DEFCONFIG) endif KERNEL_HEADER_DEFCONFIG := $(strip $(KERNEL_HEADER_DEFCONFIG)) ifeq ($(KERNEL_HEADER_DEFCONFIG),) KERNEL_HEADER_DEFCONFIG := $(KERNEL_DEFCONFIG) Loading
Documentation/devicetree/bindings/clock/qcom,gpucc.txt +2 −1 Original line number Diff line number Diff line Loading @@ -5,7 +5,8 @@ Required properties : - compatible : shall contain one of the following: "qcom,gpucc-sm8150", "qcom,gpucc-sdmshrike", "qcom,gpucc-sm6150". "qcom,gpucc-sm6150", "qcom,gpucc-sdmmagpie". - reg : shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. Loading
Documentation/devicetree/bindings/firmware/qcom,scm.txt +25 −0 Original line number Diff line number Diff line Loading @@ -12,6 +12,8 @@ Required properties: * "qcom,scm-msm8690" for MSM8690 platforms * "qcom,scm-msm8996" for MSM8996 platforms * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) * "android,firmware" for firmware image * "android,vbmeta" for setting system properties for verified boot. - clocks: One to three clocks may be required based on compatible. * No clock required for "qcom,scm-msm8996" * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" Loading @@ -28,3 +30,26 @@ Example for MSM8916: clock-names = "core", "bus", "iface"; }; }; Example for SM6150: firmware: firmware { android { compatible = "android,firmware"; vbmeta { compatible = "android,vbmeta"; parts = "vbmeta,boot,system,vendor,dtbo"; }; fstab { compatible = "android,fstab"; vendor { compatible = "android,vendor"; dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,slotselect,avb"; status = "ok"; }; }; }; };
Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt +6 −1 Original line number Diff line number Diff line Loading @@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. GPU powerlevels Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins) can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a voltage, bus, and bandwitdh level. voltage, bus, bandwidth level, and a DVM value. - qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets Loading @@ -28,3 +28,8 @@ Properties: settings) - qcom,bus-min Minimum bus level to set for the power level - qcom,bus-max maximum bus level to set for the power level - qcom,dvm-val: Value that is used as a register setting for the ACD power feature. It helps determine the threshold for when ACD activates. 0xFFFFFFFF is the default value, and the setting where ACD will never activate.
Documentation/devicetree/bindings/input/qti-haptics.txt +9 −0 Original line number Diff line number Diff line Loading @@ -130,6 +130,15 @@ waveforms/effects: [5:1]: waveform amplitude [0]: reserved. - qcom,wf-vmax-mv Usage: optional Value type: <u32> Definition: Specifies the maximum allowed output voltage in millivolts for this effect. Value specified here will be rounded off to the closest multiple of 116 mV. Allowed values: 0 to 3596. If this is not specified, the value defined in "qcom,vmax-mv" will be applied. - qcom,wf-play-rate-us Usage: optional Value type: <u32> Loading
