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Commit 8d55881c authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Tony Lindgren
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ARM: dts: dra7-evm: Add pinmux configuration for MMC



Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra74 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in dra7-evm.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 2c268d09
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+18 −4
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@

#include "dra74x.dtsi"
#include "dra7-evm-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"

/ {
	model = "TI DRA742";
@@ -326,8 +327,6 @@

&mmc1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins_default>;
	vmmc-supply = <&evm_3v3_sd>;
	vqmmc-supply = <&ldo1_reg>;
	bus-width = <4>;
@@ -336,14 +335,29 @@
	 * is always hardwired.
	 */
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
	pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
	pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};

&mmc2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins_default>;
	vmmc-supply = <&evm_1v8_sw>;
	bus-width = <8>;
	pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
	pinctrl-3 = <&mmc2_pins_ddr_rev20>;
	pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
	pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
};

&cpu0 {