Commit 8d0313ed authored Jun 19, 2018 by Steve Cohen

drm/msm/sde: set correct bit width in qseed op mode



Set the correct bit width when programming the qseed op mode
register via the reg dma path.  The logic was inverted
from what HW expects which lead to incorrect processing of
alpha blending use cases on VIG RECT0 pipes.

Change-Id: I67b10376407ab63e19168e80a714fdeaf18912c5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>

parent 9956996a

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2527,7 +2527,7 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx,

		end:
		if (sspp->layout.format) {
		if (SDE_FORMAT_IS_DX(sspp->layout.format))
		if (!SDE_FORMAT_IS_DX(sspp->layout.format))
		op_mode \|= BIT(14);
		if (sspp->layout.format->alpha_enable) {
		op_mode \|= BIT(10);