Loading drivers/usb/dwc3/core.c +28 −0 Original line number Diff line number Diff line Loading @@ -881,6 +881,34 @@ int dwc3_core_init(struct dwc3 *dwc) dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT); /* * Workaround for STAR 9001198391 which affects dwc3 core * version 3.20a only. Default HP timer value is incorrectly * set to 3us. Reprogram HP timer value to support USB 3.1 * HP timer ECN. */ if (!dwc3_is_usb31(dwc) && dwc->revision == DWC3_REVISION_320A) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); reg &= ~DWC3_GUCTL2_HP_TIMER_MASK; reg |= DWC3_GUCTL2_HP_TIMER(11); dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } /* * Workaround for STAR 9001285599 which affects dwc3 core version 3.20a * only. If the PM TIMER ECN is enabled thru GUCTL2[19], then link * compliance test (TD7.21) may fail. If the ECN is not enabled * GUCTL2[19] = 0), the controller will use the old timer value (5us), * which is still fine for Link Compliance test. Hence Do not enable * PM TIMER ECN in V3.20a by setting GUCTL2[19] by default, * instead use GUCTL2[19] = 0. */ if (dwc->revision == DWC3_REVISION_320A) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); reg &= ~DWC3_GUCTL2_LC_TIMER; dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } return 0; err3: Loading drivers/usb/dwc3/core.h +4 −0 Original line number Diff line number Diff line Loading @@ -326,6 +326,9 @@ /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) #define DWC3_GUCTL2_HP_TIMER(n) ((n) << 21) #define DWC3_GUCTL2_HP_TIMER_MASK DWC3_GUCTL2_HP_TIMER(0x1f) #define DWC3_GUCTL2_LC_TIMER (1 << 19) /* Global User Control Register 3 */ #define DWC3_GUCTL3_USB20_RETRY_DISABLE BIT(16) Loading Loading @@ -1062,6 +1065,7 @@ struct dwc3 { #define DWC3_REVISION_290A 0x5533290a #define DWC3_REVISION_300A 0x5533300a #define DWC3_REVISION_310A 0x5533310a #define DWC3_REVISION_320A 0x5533320a /* * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really Loading Loading
drivers/usb/dwc3/core.c +28 −0 Original line number Diff line number Diff line Loading @@ -881,6 +881,34 @@ int dwc3_core_init(struct dwc3 *dwc) dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT); /* * Workaround for STAR 9001198391 which affects dwc3 core * version 3.20a only. Default HP timer value is incorrectly * set to 3us. Reprogram HP timer value to support USB 3.1 * HP timer ECN. */ if (!dwc3_is_usb31(dwc) && dwc->revision == DWC3_REVISION_320A) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); reg &= ~DWC3_GUCTL2_HP_TIMER_MASK; reg |= DWC3_GUCTL2_HP_TIMER(11); dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } /* * Workaround for STAR 9001285599 which affects dwc3 core version 3.20a * only. If the PM TIMER ECN is enabled thru GUCTL2[19], then link * compliance test (TD7.21) may fail. If the ECN is not enabled * GUCTL2[19] = 0), the controller will use the old timer value (5us), * which is still fine for Link Compliance test. Hence Do not enable * PM TIMER ECN in V3.20a by setting GUCTL2[19] by default, * instead use GUCTL2[19] = 0. */ if (dwc->revision == DWC3_REVISION_320A) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); reg &= ~DWC3_GUCTL2_LC_TIMER; dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } return 0; err3: Loading
drivers/usb/dwc3/core.h +4 −0 Original line number Diff line number Diff line Loading @@ -326,6 +326,9 @@ /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) #define DWC3_GUCTL2_HP_TIMER(n) ((n) << 21) #define DWC3_GUCTL2_HP_TIMER_MASK DWC3_GUCTL2_HP_TIMER(0x1f) #define DWC3_GUCTL2_LC_TIMER (1 << 19) /* Global User Control Register 3 */ #define DWC3_GUCTL3_USB20_RETRY_DISABLE BIT(16) Loading Loading @@ -1062,6 +1065,7 @@ struct dwc3 { #define DWC3_REVISION_290A 0x5533290a #define DWC3_REVISION_300A 0x5533300a #define DWC3_REVISION_310A 0x5533310a #define DWC3_REVISION_320A 0x5533320a /* * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really Loading