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Commit 8b637ae3 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvc3/gr: update initial register/context values 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent d8b02dbb

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c

+29 −0
Original line number Original line Diff line number Diff line
@@ -1326,6 +1326,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv) 




	switch (nv_device(priv)->chipset) {

	switch (nv_device(priv)->chipset) {

	case 0xc0:

	case 0xc0:

	case 0xc3:

	case 0xd9:

	case 0xd9:

	case 0xd7:

	case 0xd7:

		break;

		break;
@@ -1473,6 +1474,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x40402c, 0x00000000);

		nv_wr32(priv, 0x40402c, 0x00000000);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		break;

		break;

	}

	}
@@ -1493,6 +1495,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x4040c8, 0xf0000087);

	nv_wr32(priv, 0x4040c8, 0xf0000087);

	switch (nv_device(priv)->chipset) {

	switch (nv_device(priv)->chipset) {

	case 0xc0:

	case 0xc0:

	case 0xc3:

	case 0xd9:

	case 0xd9:

	case 0xd7:

	case 0xd7:

		nv_wr32(priv, 0x4040d0, 0x00000000);

		nv_wr32(priv, 0x4040d0, 0x00000000);
@@ -1520,6 +1523,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) 
	case 0xd7:

	case 0xd7:

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x404174, 0x00000000);

		nv_wr32(priv, 0x404174, 0x00000000);

		break;

		break;
@@ -1662,6 +1666,7 @@ nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x405834, 0x08000000);

		nv_wr32(priv, 0x405834, 0x08000000);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x405800, 0x078000bf);

		nv_wr32(priv, 0x405800, 0x078000bf);

		nv_wr32(priv, 0x405830, 0x02180000);

		nv_wr32(priv, 0x405830, 0x02180000);
@@ -1703,6 +1708,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x4064bc, 0x00000000);

		nv_wr32(priv, 0x4064bc, 0x00000000);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		break;

		break;

	}

	}
@@ -1714,6 +1720,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x4064c4, 0x0086ffff);

		nv_wr32(priv, 0x4064c4, 0x0086ffff);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		break;

		break;

	}

	}
@@ -1753,6 +1760,7 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x408804, 0x00000040);

	nv_wr32(priv, 0x408804, 0x00000040);

	switch (nv_device(priv)->chipset) {

	switch (nv_device(priv)->chipset) {

	case 0xc0:

	case 0xc0:

	case 0xc3:

		nv_wr32(priv, 0x408808, 0x0003e00d);

		nv_wr32(priv, 0x408808, 0x0003e00d);

		nv_wr32(priv, 0x408900, 0x3080b801);

		nv_wr32(priv, 0x408900, 0x3080b801);

		nv_wr32(priv, 0x408904, 0x02000001);

		nv_wr32(priv, 0x408904, 0x02000001);
@@ -1797,6 +1805,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) 
	case 0xd7:

	case 0xd7:

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x418408, 0x00000000);

		nv_wr32(priv, 0x418408, 0x00000000);

		break;

		break;
@@ -1809,6 +1818,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x418414, 0x02200fff);

		nv_wr32(priv, 0x418414, 0x02200fff);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x418414, 0x00200fff);

		nv_wr32(priv, 0x418414, 0x00200fff);

		break;

		break;
@@ -1833,6 +1843,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x41870c, 0x00000000);

		nv_wr32(priv, 0x41870c, 0x00000000);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x41870c, 0x07c80000);

		nv_wr32(priv, 0x41870c, 0x07c80000);

		break;

		break;
@@ -1844,6 +1855,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x418800, 0x7006860a);

		nv_wr32(priv, 0x418800, 0x7006860a);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x418800, 0x0006860a);

		nv_wr32(priv, 0x418800, 0x0006860a);

		break;

		break;
@@ -1859,6 +1871,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x418830, 0x10000001);

		nv_wr32(priv, 0x418830, 0x10000001);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x418830, 0x00000001);

		nv_wr32(priv, 0x418830, 0x00000001);

		break;

		break;
@@ -1879,6 +1892,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x4188fc, 0x20100008);

		nv_wr32(priv, 0x4188fc, 0x20100008);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x4188fc, 0x00100000);

		nv_wr32(priv, 0x4188fc, 0x00100000);

		break;

		break;
@@ -1902,6 +1916,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x418b00, 0x00000006);

		nv_wr32(priv, 0x418b00, 0x00000006);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x418b00, 0x00000000);

		nv_wr32(priv, 0x418b00, 0x00000000);

		break;

		break;
@@ -1929,6 +1944,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x418c6c, 0x00000001);

		nv_wr32(priv, 0x418c6c, 0x00000001);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		break;

		break;

	}

	}
@@ -1954,6 +1970,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x419864, 0x00000129);

		nv_wr32(priv, 0x419864, 0x00000129);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x419864, 0x0000012a);

		nv_wr32(priv, 0x419864, 0x0000012a);

		break;

		break;
@@ -1968,6 +1985,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
	switch (nv_device(priv)->chipset) {

	switch (nv_device(priv)->chipset) {

	case 0xc0:

	case 0xc0:

		break;

		break;

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x419a1c, 0x00000000);

		nv_wr32(priv, 0x419a1c, 0x00000000);

		nv_wr32(priv, 0x419a20, 0x00000800);

		nv_wr32(priv, 0x419a20, 0x00000800);
@@ -1981,6 +1999,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
	case 0xd7:

	case 0xd7:

		nv_wr32(priv, 0x00419ac4, 0x0017f440);

		nv_wr32(priv, 0x00419ac4, 0x0017f440);

		break;

		break;

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x00419ac4, 0x0007f440);

		nv_wr32(priv, 0x00419ac4, 0x0007f440);

		break;

		break;
@@ -1999,6 +2018,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x419be0, 0x00400001);

		nv_wr32(priv, 0x419be0, 0x00400001);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x419be0, 0x00000001);

		nv_wr32(priv, 0x419be0, 0x00000001);

		break;

		break;
@@ -2010,6 +2030,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x419c00, 0x0000000a);

		nv_wr32(priv, 0x419c00, 0x0000000a);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x419c00, 0x00000002);

		nv_wr32(priv, 0x419c00, 0x00000002);

		break;

		break;
@@ -2018,6 +2039,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x419c08, 0x00000002);

	nv_wr32(priv, 0x419c08, 0x00000002);

	nv_wr32(priv, 0x419c20, 0x00000000);

	nv_wr32(priv, 0x419c20, 0x00000000);

	switch (nv_device(priv)->chipset) {

	switch (nv_device(priv)->chipset) {

	case 0xc3:

	case 0xce:

	case 0xce:

	case 0xcf:

	case 0xcf:

		nv_wr32(priv, 0x419cb0, 0x00020048);

		nv_wr32(priv, 0x419cb0, 0x00020048);
@@ -2042,6 +2064,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x419d20, 0x12180000);

		nv_wr32(priv, 0x419d20, 0x12180000);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x419d20, 0x02180000);

		nv_wr32(priv, 0x419d20, 0x02180000);

		break;

		break;
@@ -2054,6 +2077,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x419d44, 0x02180218);

		nv_wr32(priv, 0x419d44, 0x02180218);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		break;

		break;

	}

	}
@@ -2090,6 +2114,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
	case 0xd7:

	case 0xd7:

		nv_wr32(priv, 0x419ee0, 0x00010110);

		nv_wr32(priv, 0x419ee0, 0x00010110);

		break;

		break;

	case 0xc3:

	default:

	default:

		nv_wr32(priv, 0x419ee0, 0x00011110);

		nv_wr32(priv, 0x419ee0, 0x00011110);

		break;

		break;
@@ -2100,6 +2125,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 
		nv_wr32(priv, 0x419f50, 0x00000000);

		nv_wr32(priv, 0x419f50, 0x00000000);

		nv_wr32(priv, 0x419f54, 0x00000000);

		nv_wr32(priv, 0x419f54, 0x00000000);

		break;

		break;

	case 0xc3:

	case 0xd9:

	case 0xd9:

	case 0xd7:

	case 0xd7:

		nv_wr32(priv, 0x419f30, 0x00000000);

		nv_wr32(priv, 0x419f30, 0x00000000);
@@ -2436,6 +2462,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) 
			nv_icmd(priv, i, 0x00000040);

			nv_icmd(priv, i, 0x00000040);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

	default:

	default:

		break;

		break;

	}

	}
@@ -2454,6 +2481,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) 
			nv_icmd(priv, i, 0x0000c080);

			nv_icmd(priv, i, 0x0000c080);

		break;

		break;

	case 0xc0:

	case 0xc0:

	case 0xc3:

		break;

		break;

	default:

	default:

		break;

		break;
@@ -3282,6 +3310,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) 




	switch (nv_device(priv)->chipset) {

	switch (nv_device(priv)->chipset) {

	case 0xc0:

	case 0xc0:

	case 0xc3:

		nv_mthd(priv, 0x902d, 0x3410, 0x00000000);

		nv_mthd(priv, 0x902d, 0x3410, 0x00000000);

		break;

		break;

	case 0xd9:

	case 0xd9:

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc

+29 −4
Original line number Original line Diff line number Diff line
@@ -58,10 +58,10 @@ chipsets: 
.b16 #nvc0_tpc_mmio_head

.b16 #nvc0_tpc_mmio_head

.b16 #nvc1_tpc_mmio_tail

.b16 #nvc1_tpc_mmio_tail

.b8  0xc3 0 0 0

.b8  0xc3 0 0 0

.b16 #nvc0_gpc_mmio_head

.b16 #nnvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_tail

.b16 #nnvc0_gpc_mmio_tail

.b16 #nvc0_tpc_mmio_head

.b16 #nnvc3_tpc_mmio_head

.b16 #nvc3_tpc_mmio_tail

.b16 #nnvc3_tpc_mmio_tail

.b8  0xc4 0 0 0

.b8  0xc4 0 0 0

.b16 #nvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_tail

.b16 #nvc0_gpc_mmio_tail
@@ -234,6 +234,31 @@ mmctx_data(0x000698, 1) 
mmctx_data(0x000750, 2)

mmctx_data(0x000750, 2)

nnvc0_tpc_mmio_tail:

nnvc0_tpc_mmio_tail:





nnvc3_tpc_mmio_head:

mmctx_data(0x000018, 1)

mmctx_data(0x00003c, 1)

mmctx_data(0x000048, 1)

mmctx_data(0x000064, 1)

mmctx_data(0x000088, 1)

mmctx_data(0x000200, 6)

mmctx_data(0x00021c, 2)

mmctx_data(0x0002c4, 1)

mmctx_data(0x000300, 6)

mmctx_data(0x0003d0, 1)

mmctx_data(0x0003e0, 2)

mmctx_data(0x000400, 3)

mmctx_data(0x000420, 1)

mmctx_data(0x0004b0, 1)

mmctx_data(0x0004e8, 1)

mmctx_data(0x0004f4, 1)

mmctx_data(0x000520, 2)

mmctx_data(0x000604, 4)

mmctx_data(0x000644, 20)

mmctx_data(0x000698, 1)

mmctx_data(0x0006e0, 1)

mmctx_data(0x000730, 11)

nnvc3_tpc_mmio_tail:



nvd9_tpc_mmio_head:

nvd9_tpc_mmio_head:

mmctx_data(0x000018, 1)

mmctx_data(0x000018, 1)

mmctx_data(0x00003c, 1)

mmctx_data(0x00003c, 1)

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h

+29 −5
Original line number Original line Diff line number Diff line
@@ -40,8 +40,8 @@ uint32_t nvc0_grgpc_data[] = { 
	0x013800d4,

	0x013800d4,

	0x02640200,

	0x02640200,

	0x000000c3,

	0x000000c3,

	0x013400d4,

	0x01980138,

	0x02600200,

	0x030802b0,

	0x000000c4,

	0x000000c4,

	0x013400d4,

	0x013400d4,

	0x02600200,

	0x02600200,
@@ -56,10 +56,10 @@ uint32_t nvc0_grgpc_data[] = { 
	0x025c0200,

	0x025c0200,

	0x000000d9,

	0x000000d9,

	0x02000198,

	0x02000198,

	0x030c02b0,

	0x03640308,

	0x000000d7,

	0x000000d7,

	0x02000198,

	0x02000198,

	0x030c02b0,

	0x03640308,

	0x00000000,

	0x00000000,

/* 0x00d4: nvc0_gpc_mmio_head */

/* 0x00d4: nvc0_gpc_mmio_head */

	0x00000380,

	0x00000380,
@@ -194,7 +194,31 @@ uint32_t nvc0_grgpc_data[] = { 
	0x00000698,

	0x00000698,

	0x04000750,

	0x04000750,

/* 0x02b0: nnvc0_tpc_mmio_tail */

/* 0x02b0: nnvc0_tpc_mmio_tail */

/* 0x02b0: nvd9_tpc_mmio_head */

/* 0x02b0: nnvc3_tpc_mmio_head */

	0x00000018,

	0x0000003c,

	0x00000048,

	0x00000064,

	0x00000088,

	0x14000200,

	0x0400021c,

	0x000002c4,

	0x14000300,

	0x000003d0,

	0x040003e0,

	0x08000400,

	0x00000420,

	0x000004b0,

	0x000004e8,

	0x000004f4,

	0x04000520,

	0x0c000604,

	0x4c000644,

	0x00000698,

	0x000006e0,

	0x28000730,

/* 0x0308: nnvc3_tpc_mmio_tail */

/* 0x0308: nvd9_tpc_mmio_head */

	0x00000018,

	0x00000018,

	0x0000003c,

	0x0000003c,

	0x00000048,

	0x00000048,

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc

+2 −2
Original line number Original line Diff line number Diff line
@@ -54,8 +54,8 @@ chipsets: 
.b16 #nvc0_hub_mmio_head

.b16 #nvc0_hub_mmio_head

.b16 #nvc1_hub_mmio_tail

.b16 #nvc1_hub_mmio_tail

.b8  0xc3 0 0 0

.b8  0xc3 0 0 0

.b16 #nvc0_hub_mmio_head

.b16 #nnvc0_hub_mmio_head

.b16 #nvc0_hub_mmio_tail

.b16 #nnvc0_hub_mmio_tail

.b8  0xc4 0 0 0

.b8  0xc4 0 0 0

.b16 #nvc0_hub_mmio_head

.b16 #nvc0_hub_mmio_head

.b16 #nvc0_hub_mmio_tail

.b16 #nvc0_hub_mmio_tail

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -207,7 +207,7 @@ uint32_t nvc0_grhub_data[] = { 
	0x000000c1,

	0x000000c1,

	0x03ec034c,

	0x03ec034c,

	0x000000c3,

	0x000000c3,

	0x03e8034c,

	0x048803ec,

	0x000000c4,

	0x000000c4,

	0x03e8034c,

	0x03e8034c,

	0x000000c8,

	0x000000c8,